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Searched refs:UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h771 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 macro
H A Duvd_6_0_sh_mask.h769 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h517 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_2_5_sh_mask.h2148 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3274 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3819 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2893 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3502 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3812 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3946 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro
H A Dvcn_4_0_3_sh_mask.h3981 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK … macro