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Searched refs:UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h775 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 macro
H A Duvd_6_0_sh_mask.h773 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h519 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_2_5_sh_mask.h2150 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3276 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3821 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2895 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3504 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3814 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3948 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro
H A Dvcn_4_0_3_sh_mask.h3983 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK … macro