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Searched refs:UVD_SUVD_CGC_GATE__SRE_HEVC_MASK (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v6_0.c671 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
704 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1294 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | in uvd_v6_0_enable_clock_gating()
H A Dvcn_v4_0_5.c747 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
H A Dvcn_v4_0_3.c689 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK in vcn_v4_0_3_disable_clock_gating_dpg_mode()
H A Dvcn_v1_0.c582 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK in vcn_v1_0_disable_clock_gating()
H A Dvcn_v2_0.c609 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK in vcn_v2_0_disable_clock_gating()
H A Dvcn_v2_5.c843 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK in vcn_v2_6_enable_ras()
H A Dvcn_v4_0.c820 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
H A Dvcn_v3_0.c846 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK in vcn_v3_0_disable_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h232 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Duvd_5_0_sh_mask.h735 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 macro
H A Duvd_6_0_sh_mask.h737 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h460 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_2_5_sh_mask.h2089 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3215 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3760 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2825 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_5_0_0_sh_mask.h1147 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_4_0_5_sh_mask.h1338 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_4_0_0_sh_mask.h1342 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro
H A Dvcn_4_0_3_sh_mask.h1342 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK … macro