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Searched refs:UVD_SUVD_CGC_GATE__SRE_H264_MASK (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h231 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Duvd_5_0_sh_mask.h733 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 macro
H A Duvd_6_0_sh_mask.h735 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h459 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_2_5_sh_mask.h2088 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3214 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3759 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2824 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_5_0_0_sh_mask.h1146 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_4_0_5_sh_mask.h1337 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_4_0_0_sh_mask.h1341 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Dvcn_4_0_3_sh_mask.h1341 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c711 | UVD_SUVD_CGC_GATE__SRE_H264_MASK in vcn_v4_0_5_disable_clock_gating()
H A Dvcn_v2_0.c602 | UVD_SUVD_CGC_GATE__SRE_H264_MASK in vcn_v2_0_disable_clock_gating()
H A Dvcn_v1_0.c575 | UVD_SUVD_CGC_GATE__SRE_H264_MASK in vcn_v1_0_disable_clock_gating()
H A Dvcn_v2_5.c692 | UVD_SUVD_CGC_GATE__SRE_H264_MASK in vcn_v2_5_disable_clock_gating()
H A Dvcn_v3_0.c810 | UVD_SUVD_CGC_GATE__SRE_H264_MASK in vcn_v3_0_disable_clock_gating()