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Searched refs:UVD_SEMA_CMD__WR_PHASE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 macro
H A Duvd_4_2_sh_mask.h34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 macro
H A Duvd_4_0_sh_mask.h623 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x00000004 macro
H A Duvd_5_0_sh_mask.h34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 macro
H A Duvd_6_0_sh_mask.h34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h293 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2952 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h3153 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h3284 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h4040 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h4144 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4284 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4327 #define UVD_SEMA_CMD__WR_PHASE__SHIFT … macro