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Searched refs:UVD_SEMA_CMD__WR_PHASE_MASK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 macro
H A Duvd_4_2_sh_mask.h33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 macro
H A Duvd_4_0_sh_mask.h622 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L macro
H A Duvd_5_0_sh_mask.h33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 macro
H A Duvd_6_0_sh_mask.h33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h298 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro
H A Dvcn_2_5_sh_mask.h2957 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3158 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3289 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h4045 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4149 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4289 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4332 #define UVD_SEMA_CMD__WR_PHASE_MASK … macro