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Searched refs:UVD_POWER_STATUS__UVD_POWER_STATUS_MASK (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c608 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v4_0_5_enable_static_power_gating()
879 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_start_dpg_mode()
1186 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_stop_dpg_mode()
1193 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_stop_dpg_mode()
1310 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_pause_dpg_mode()
1324 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_pause_dpg_mode()
1636 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_5_print_ip_state()
1668 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_5_dump_ip_state()
H A Dvcn_v2_5.c873 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_start_dpg_mode()
1028 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_start()
1404 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_stop_dpg_mode()
1417 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_stop_dpg_mode()
1484 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, in vcn_v2_5_stop()
1485 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_stop()
1510 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_pause_dpg_mode()
1555 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_pause_dpg_mode()
1561 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_pause_dpg_mode()
1946 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v2_5_print_ip_state()
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H A Dvcn_v1_0.c788 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_1_0_enable_static_power_gating()
1213 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_stop_dpg_mode()
1230 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_stop_dpg_mode()
1275 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1305 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1331 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1366 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1946 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v1_0_print_ip_state()
1978 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v1_0_dump_ip_state()
H A Dvcn_v3_0.c695 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v3_0_enable_static_power_gating()
993 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_start_dpg_mode()
1544 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_stop_dpg_mode()
1557 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_stop_dpg_mode()
1658 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_pause_dpg_mode()
1709 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_pause_dpg_mode()
2272 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v3_0_print_ip_state()
2304 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v3_0_dump_ip_state()
H A Dvcn_v2_0.c805 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v2_0_enable_static_power_gating()
1153 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_stop_dpg_mode()
1166 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_stop_dpg_mode()
1259 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_pause_dpg_mode()
1307 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_pause_dpg_mode()
2054 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v2_0_print_ip_state()
2086 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v2_0_dump_ip_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h36 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Duvd_3_1_sh_mask.h737 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 macro
H A Duvd_4_2_sh_mask.h743 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 macro
H A Duvd_4_0_sh_mask.h584 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L macro
H A Duvd_5_0_sh_mask.h927 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 macro
H A Duvd_6_0_sh_mask.h915 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h80 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_2_5_sh_mask.h1520 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1517 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2958 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2054 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_5_0_0_sh_mask.h5351 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_4_0_5_sh_mask.h6174 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_4_0_0_sh_mask.h6347 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro
H A Dvcn_4_0_3_sh_mask.h7151 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK … macro