UVD_POWER_STATUS__UVD_PG_MODE_MASK (reference) in projects: linux

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Searched refs:UVD_POWER_STATUS__UVD_PG_MODE_MASK (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A D	uvd_7_0_sh_mask.h	`37 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	uvd_5_0_sh_mask.h	`929 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro`
H A D	uvd_6_0_sh_mask.h	`917 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro`
/linux/drivers/gpu/drm/amd/amdgpu/
H A D	vcn_v5_0_0.c	`674 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v5_0_0_start_dpg_mode() 931 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v5_0_0_stop_dpg_mode()`
H A D	vcn_v4_0_5.c	`884 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v4_0_5_start_dpg_mode() 1199 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v4_0_5_stop_dpg_mode()`
H A D	vcn_v4_0_3.c	`775 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v4_0_3_start_dpg_mode() 1286 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v4_0_3_stop_dpg_mode()`
H A D	vcn_v2_0.c	`849 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v2_0_start_dpg_mode() 1172 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v2_0_stop_dpg_mode()`
H A D	vcn_v4_0.c	`970 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v4_0_start_dpg_mode() 1536 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v4_0_stop_dpg_mode()`
H A D	vcn_v1_0.c	`1017 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v1_0_start_dpg_mode() 1235 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v1_0_stop_dpg_mode()`
H A D	vcn_v2_5.c	`878 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v2_5_start_dpg_mode() 1423 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v2_5_stop_dpg_mode()`
H A D	vcn_v3_0.c	`998 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; in vcn_v3_0_start_dpg_mode() 1563 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in vcn_v3_0_stop_dpg_mode()`
H A D	uvd_v6_0.c	`734 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in uvd_v6_0_start()`
H A D	uvd_v7_0.c	`966 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in uvd_v7_0_start()`
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A D	vcn_1_0_sh_mask.h	`81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_2_5_sh_mask.h	`1521 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_2_0_0_sh_mask.h	`1518 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_2_6_0_sh_mask.h	`2959 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_3_0_0_sh_mask.h	`2055 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_5_0_0_sh_mask.h	`5352 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_4_0_5_sh_mask.h	`6175 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_4_0_0_sh_mask.h	`6348 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`
H A D	vcn_4_0_3_sh_mask.h	`7152 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro`