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Searched refs:UVD_POWER_STATUS__UVD_PG_EN_MASK (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h42 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Duvd_5_0_sh_mask.h939 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 macro
H A Duvd_6_0_sh_mask.h927 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c603 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v5_0_0_enable_static_power_gating()
722 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v5_0_0_start_dpg_mode()
H A Dvcn_v4_0_5.c622 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_5_enable_static_power_gating()
923 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_5_start_dpg_mode()
H A Dvcn_v1_0.c786 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_1_0_enable_static_power_gating()
1030 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_0.c799 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_0_enable_static_power_gating()
859 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_0_start_dpg_mode()
H A Dvcn_v4_0.c679 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_enable_static_power_gating()
1019 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_start_dpg_mode()
H A Dvcn_v3_0.c715 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v3_0_enable_static_power_gating()
1038 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v3_0_start_dpg_mode()
H A Duvd_v6_0.c1487 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); in uvd_v6_0_set_powergating_state()
H A Dvcn_v4_0_3.c849 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_3_start_dpg_mode()
H A Dvcn_v2_5.c1031 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_5_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h83 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_2_5_sh_mask.h1523 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1520 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2961 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2057 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_5_0_0_sh_mask.h5354 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_4_0_5_sh_mask.h6177 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_4_0_0_sh_mask.h6350 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_4_0_3_sh_mask.h7154 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro