Searched refs:UVD_MPC_SET_MUX__SET_1__SHIFT (Results 1 – 21 of 21) sorted by relevance
635 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
512 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
516 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
529 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003 macro
548 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
550 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
1142 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
2883 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
2648 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
2875 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
3956 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
4073 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
4206 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
4249 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
938 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v4_0_5_start_dpg_mode()1077 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v4_0_5_start()
837 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v4_0_3_start_dpg_mode()1163 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v4_0_3_start()
903 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_0_start_dpg_mode()1036 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_0_start()
1023 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v4_0_start_dpg_mode()1165 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v4_0_start()
885 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v1_0_start_spg_mode()1068 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v1_0_start_dpg_mode()
932 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_5_start_dpg_mode()1086 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_5_start()
1052 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v3_0_start_dpg_mode()1216 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v3_0_start()