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Searched refs:UVD_MPC_SET_MUX__SET_1_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h638 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Duvd_3_1_sh_mask.h511 #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 macro
H A Duvd_4_2_sh_mask.h515 #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 macro
H A Duvd_4_0_sh_mask.h528 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L macro
H A Duvd_5_0_sh_mask.h547 #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 macro
H A Duvd_6_0_sh_mask.h549 #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1145 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Dvcn_2_5_sh_mask.h2886 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2651 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2878 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3959 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4076 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4209 #define UVD_MPC_SET_MUX__SET_1_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4252 #define UVD_MPC_SET_MUX__SET_1_MASK … macro