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Searched refs:UVD_MPC_SET_MUX__SET_0_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h637 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Duvd_3_1_sh_mask.h509 #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 macro
H A Duvd_4_2_sh_mask.h513 #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 macro
H A Duvd_4_0_sh_mask.h526 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L macro
H A Duvd_5_0_sh_mask.h545 #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 macro
H A Duvd_6_0_sh_mask.h547 #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1144 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Dvcn_2_5_sh_mask.h2885 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2650 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2877 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3958 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4075 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4208 #define UVD_MPC_SET_MUX__SET_0_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4251 #define UVD_MPC_SET_MUX__SET_0_MASK … macro