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Searched refs:UVD_MPC_SET_MUXB1__VARB_6__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h628 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Duvd_3_1_sh_mask.h506 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 macro
H A Duvd_4_2_sh_mask.h510 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 macro
H A Duvd_4_0_sh_mask.h523 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x00000006 macro
H A Duvd_5_0_sh_mask.h542 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 macro
H A Duvd_6_0_sh_mask.h544 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1135 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2876 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2641 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2868 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3949 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h4066 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4199 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4242 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT … macro