Home
last modified time | relevance | path

Searched refs:UVD_MPC_SET_MUXB1__VARB_5__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h627 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Duvd_3_1_sh_mask.h504 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h508 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 macro
H A Duvd_4_0_sh_mask.h521 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x00000000 macro
H A Duvd_5_0_sh_mask.h540 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h542 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1134 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2875 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2640 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2867 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3948 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h4065 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4198 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4241 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT … macro