Searched refs:UVD_MPC_SET_MUXB0__VARB_4__SHIFT (Results 1 – 21 of 21) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_7_0_sh_mask.h | 620 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | uvd_3_1_sh_mask.h | 502 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
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| H A D | uvd_4_2_sh_mask.h | 506 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
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| H A D | uvd_4_0_sh_mask.h | 519 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018 macro
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| H A D | uvd_5_0_sh_mask.h | 538 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
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| H A D | uvd_6_0_sh_mask.h | 540 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_sh_mask.h | 1127 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | vcn_2_5_sh_mask.h | 2868 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | vcn_2_0_0_sh_mask.h | 2633 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | vcn_2_6_0_sh_mask.h | 2860 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | vcn_3_0_0_sh_mask.h | 3941 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | vcn_4_0_5_sh_mask.h | 4058 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | vcn_4_0_0_sh_mask.h | 4191 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| H A D | vcn_4_0_3_sh_mask.h | 4234 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v4_0_5.c | 971 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_5_start_dpg_mode()
1109 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v4_0_5_start()
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| H A D | vcn_v4_0_3.c | 905 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
1229 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v4_0_3_start()
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| H A D | vcn_v1_0.c | 892 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v1_0_start_spg_mode()
1076 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
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| H A D | vcn_v2_0.c | 907 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v2_0_start_dpg_mode()
1041 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v2_0_start()
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| H A D | vcn_v2_5.c | 1079 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v2_5_start()
1231 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v2_5_mmsch_start()
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| H A D | vcn_v4_0.c | 1066 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_start_dpg_mode()
1207 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v4_0_start()
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| H A D | vcn_v3_0.c | 1086 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v3_0_start_dpg_mode()
1249 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); in vcn_v3_0_start()
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