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Searched refs:UVD_MPC_SET_MUXB0__VARB_2__SHIFT (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h618 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Duvd_3_1_sh_mask.h498 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
H A Duvd_4_2_sh_mask.h502 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
H A Duvd_4_0_sh_mask.h515 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c macro
H A Duvd_5_0_sh_mask.h534 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
H A Duvd_6_0_sh_mask.h536 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1125 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2866 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2631 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2858 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3939 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h4056 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4189 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4232 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c969 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v4_0_5_start_dpg_mode()
1107 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c903 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v4_0_3_start_dpg_mode()
1227 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v4_0_3_start()
H A Dvcn_v1_0.c890 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v1_0_start_spg_mode()
1074 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_0.c905 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_0_start_dpg_mode()
1039 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_0_start()
H A Dvcn_v2_5.c1077 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_5_start()
1229 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v2_5_mmsch_start()
H A Dvcn_v4_0.c1064 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v4_0_start_dpg_mode()
1205 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v4_0_start()
H A Dvcn_v3_0.c1084 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v3_0_start_dpg_mode()
1247 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | in vcn_v3_0_start()