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Searched refs:UVD_MPC_SET_MUXB0__VARB_1_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h622 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Duvd_3_1_sh_mask.h495 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 macro
H A Duvd_4_2_sh_mask.h499 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 macro
H A Duvd_4_0_sh_mask.h512 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000fc0L macro
H A Duvd_5_0_sh_mask.h531 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 macro
H A Duvd_6_0_sh_mask.h533 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1129 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Dvcn_2_5_sh_mask.h2870 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2635 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2862 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3943 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4060 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4193 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4236 #define UVD_MPC_SET_MUXB0__VARB_1_MASK … macro