Searched refs:UVD_MPC_SET_MUXA0__VARA_2__SHIFT (Results 1 – 19 of 19) sorted by relevance
600 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
482 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
486 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
499 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c macro
518 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
520 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
1107 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
2848 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
2613 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
2840 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
3921 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
4038 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
4171 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
4214 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
922 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v4_0_5_start_dpg_mode()1061 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v4_0_5_start()
887 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_0_start_dpg_mode()1020 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_0_start()
872 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v1_0_start_spg_mode()1055 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v1_0_start_dpg_mode()
916 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_5_start_dpg_mode()1070 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_5_start()
1036 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v3_0_start_dpg_mode()1200 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v3_0_start()