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Searched refs:UVD_MPC_SET_MUXA0__VARA_1__SHIFT (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h599 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Duvd_3_1_sh_mask.h480 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
H A Duvd_4_2_sh_mask.h484 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
H A Duvd_4_0_sh_mask.h497 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006 macro
H A Duvd_5_0_sh_mask.h516 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
H A Duvd_6_0_sh_mask.h518 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1106 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2847 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2612 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2839 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3920 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h4037 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4170 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4213 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c961 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_5_start_dpg_mode()
1099 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c895 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_3_start_dpg_mode()
1219 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_3_start()
H A Dvcn_v1_0.c883 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v1_0_start_spg_mode()
1067 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_0.c897 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_0_start_dpg_mode()
1031 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_0_start()
H A Dvcn_v2_5.c1069 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_start()
1221 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_mmsch_start()
H A Dvcn_v4_0.c1056 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_start_dpg_mode()
1197 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_start()
H A Dvcn_v3_0.c1076 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v3_0_start_dpg_mode()
1239 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v3_0_start()