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Searched refs:UVD_MPC_SET_MUXA0__VARA_0_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h603 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Duvd_3_1_sh_mask.h477 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
H A Duvd_4_2_sh_mask.h481 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
H A Duvd_4_0_sh_mask.h494 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL macro
H A Duvd_5_0_sh_mask.h513 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
H A Duvd_6_0_sh_mask.h515 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1110 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Dvcn_2_5_sh_mask.h2851 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2616 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2843 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3924 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4041 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4174 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4217 #define UVD_MPC_SET_MUXA0__VARA_0_MASK … macro