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Searched refs:UVD_MPC_CNTL__REPLACEMENT_MODE_MASK (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h467 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 macro
H A Duvd_4_2_sh_mask.h471 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 macro
H A Duvd_4_0_sh_mask.h486 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L macro
H A Duvd_5_0_sh_mask.h503 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 macro
H A Duvd_6_0_sh_mask.h505 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1103 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h2836 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2601 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2828 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3909 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4026 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4159 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4200 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c1054 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; in vcn_v4_0_5_start()
H A Dvcn_v2_0.c1013 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; in vcn_v2_0_start()
H A Dvcn_v1_0.c866 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; in vcn_v1_0_start_spg_mode()
H A Dvcn_v2_5.c1063 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; in vcn_v2_5_start()
H A Dvcn_v3_0.c1193 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; in vcn_v3_0_start()