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Searched refs:UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h381 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 macro
H A Duvd_4_2_sh_mask.h385 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 macro
H A Duvd_4_0_sh_mask.h381 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L macro
H A Duvd_5_0_sh_mask.h417 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 macro
H A Duvd_6_0_sh_mask.h419 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1064 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_2_5_sh_mask.h3401 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2450 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_2_6_0_sh_mask.h996 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_3_0_0_sh_mask.h4723 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_5_0_0_sh_mask.h4285 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4713 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4872 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4915 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c1233 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; in vcn_v4_0_5_stop()
H A Dvcn_v2_0.c1195 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; in vcn_v2_0_stop()
H A Dvcn_v1_0.c1169 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; in vcn_v1_0_stop_spg_mode()
H A Dvcn_v2_5.c1447 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; in vcn_v2_5_stop()
H A Dvcn_v3_0.c1588 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; in vcn_v3_0_stop()