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Searched refs:UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h527 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Duvd_3_1_sh_mask.h363 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 macro
H A Duvd_4_2_sh_mask.h367 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 macro
H A Duvd_4_0_sh_mask.h344 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L macro
H A Duvd_5_0_sh_mask.h399 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 macro
H A Duvd_6_0_sh_mask.h401 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c857 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); in vcn_v1_0_start_spg_mode()
1038 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in vcn_v1_0_start_dpg_mode()
1093 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v4_0_5.c909 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in vcn_v4_0_5_start_dpg_mode()
1050 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); in vcn_v4_0_5_start()
H A Duvd_v7_0.c894 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in uvd_v7_0_sriov_start()
1009 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in uvd_v7_0_start()
H A Dvcn_v2_0.c874 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in vcn_v2_0_start_dpg_mode()
1009 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); in vcn_v2_0_start()
H A Dvcn_v2_5.c903 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in vcn_v2_5_start_dpg_mode()
1059 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); in vcn_v2_5_start()
H A Dvcn_v3_0.c1023 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | in vcn_v3_0_start_dpg_mode()
1189 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); in vcn_v3_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1049 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_2_5_sh_mask.h3371 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_2_0_0_sh_mask.h2420 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_2_6_0_sh_mask.h964 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_3_0_0_sh_mask.h4687 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_5_0_0_sh_mask.h4254 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_4_0_5_sh_mask.h4681 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_4_0_0_sh_mask.h4840 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro
H A Dvcn_4_0_3_sh_mask.h4883 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK macro