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Searched refs:UVD_LMI_CTRL2__STALL_ARB_UMC_MASK (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v7_0.c875 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in uvd_v7_0_sriov_start()
876 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_sriov_start()
932 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); in uvd_v7_0_sriov_start()
988 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in uvd_v7_0_start()
989 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_start()
1039 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_start()
1151 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in uvd_v7_0_stop()
1152 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_stop()
1165 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in uvd_v7_0_stop()
H A Dvcn_v1_0.c902 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v1_0_start_spg_mode()
1174 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, in vcn_v1_0_stop_spg_mode()
1175 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v1_0_stop_spg_mode()
H A Dvcn_v4_0_5.c1037 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v4_0_5_start()
1240 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v4_0_5_stop()
H A Dvcn_v2_0.c1045 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v2_0_start()
1202 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v2_0_stop()
H A Dvcn_v2_5.c1102 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v2_5_start()
1454 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v2_5_stop()
H A Dvcn_v3_0.c1176 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); in vcn_v3_0_start()
1595 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; in vcn_v3_0_stop()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h481 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Duvd_3_1_sh_mask.h309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
H A Duvd_4_2_sh_mask.h309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
H A Duvd_4_0_sh_mask.h312 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L macro
H A Duvd_5_0_sh_mask.h341 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
H A Duvd_6_0_sh_mask.h343 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h999 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_2_5_sh_mask.h3310 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2072 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_2_6_0_sh_mask.h899 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_3_0_0_sh_mask.h4622 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_5_0_0_sh_mask.h4190 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4618 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4775 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4818 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK … macro