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Searched refs:UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h113 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Duvd_3_1_sh_mask.h42 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h42 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 macro
H A Duvd_4_0_sh_mask.h250 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x00000000 macro
H A Duvd_5_0_sh_mask.h42 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h42 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h303 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2192 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h3163 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h3863 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h2958 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_5_0_0_sh_mask.h3526 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h3836 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h3970 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4005 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT … macro