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Searched refs:UVD_CGC_UDEC_STATUS__CM_VCLK_MASK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h277 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
H A Duvd_4_2_sh_mask.h277 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
H A Duvd_4_0_sh_mask.h212 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L macro
H A Duvd_5_0_sh_mask.h301 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
H A Duvd_6_0_sh_mask.h303 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2046 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1998 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3717 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2776 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3450 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3760 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3894 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro
H A Dvcn_4_0_3_sh_mask.h3929 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK … macro