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Searched refs:UVD_CGC_GATE__UDEC_RE_MASK (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h409 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Duvd_3_1_sh_mask.h147 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
H A Duvd_4_2_sh_mask.h147 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
H A Duvd_4_0_sh_mask.h111 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L macro
H A Duvd_5_0_sh_mask.h159 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
H A Duvd_6_0_sh_mask.h161 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h837 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_2_5_sh_mask.h1907 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1856 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3578 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2637 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_5_0_0_sh_mask.h72 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_4_0_5_sh_mask.h68 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h72 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h72 #define UVD_CGC_GATE__UDEC_RE_MASK … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c670 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v4_0_5_disable_clock_gating()
H A Dvcn_v2_0.c562 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v2_0_disable_clock_gating()
H A Dvcn_v1_0.c535 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v1_0_disable_clock_gating()
H A Dvcn_v2_5.c649 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v2_5_disable_clock_gating()
H A Dvcn_v3_0.c768 | UVD_CGC_GATE__UDEC_RE_MASK in vcn_v3_0_disable_clock_gating()