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Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c544 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_disable_clock_gating()
646 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
648 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
704 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_enable_clock_gating()
706 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_enable_clock_gating()
H A Dvcn_v1_0.c515 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_disable_clock_gating()
639 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_enable_clock_gating()
641 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_enable_clock_gating()
700 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
702 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_5.c631 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_disable_clock_gating()
737 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
739 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
796 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_enable_clock_gating()
798 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_enable_clock_gating()
H A Dvcn_v3_0.c750 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_disable_clock_gating()
878 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
880 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
934 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_enable_clock_gating()
936 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_enable_clock_gating()
H A Dvcn_v4_0_5.c767 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_5_disable_clock_gating_dpg_mode()
822 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_5_enable_clock_gating()
H A Dvcn_v4_0_3.c669 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_3_disable_clock_gating_dpg_mode()
721 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_3_enable_clock_gating()
H A Dvcn_v4_0.c831 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_disable_clock_gating_dpg_mode()
886 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_enable_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h418 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Duvd_3_1_sh_mask.h222 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h222 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
H A Duvd_4_0_sh_mask.h37 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000 macro
H A Duvd_5_0_sh_mask.h242 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h244 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h911 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_2_5_sh_mask.h1979 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h1929 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h3650 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h2709 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_5_0_0_sh_mask.h87 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h83 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h87 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h87 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro