1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the TI TPS23881 PoE PSE Controller driver (I2C bus)
4 *
5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/firmware.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pse-pd/pse.h>
17
18 #define TPS23881_MAX_CHANS 8
19
20 #define TPS23881_REG_PW_STATUS 0x10
21 #define TPS23881_REG_OP_MODE 0x12
22 #define TPS23881_OP_MODE_SEMIAUTO 0xaaaa
23 #define TPS23881_REG_DIS_EN 0x13
24 #define TPS23881_REG_DET_CLA_EN 0x14
25 #define TPS23881_REG_GEN_MASK 0x17
26 #define TPS23881_REG_NBITACC BIT(5)
27 #define TPS23881_REG_PW_EN 0x19
28 #define TPS23881_REG_PORT_MAP 0x26
29 #define TPS23881_REG_PORT_POWER 0x29
30 #define TPS23881_REG_POEPLUS 0x40
31 #define TPS23881_REG_TPON BIT(0)
32 #define TPS23881_REG_FWREV 0x41
33 #define TPS23881_REG_DEVID 0x43
34 #define TPS23881_REG_DEVID_MASK 0xF0
35 #define TPS23881_DEVICE_ID 0x02
36 #define TPS23881_REG_SRAM_CTRL 0x60
37 #define TPS23881_REG_SRAM_DATA 0x61
38
39 struct tps23881_port_desc {
40 u8 chan[2];
41 bool is_4p;
42 };
43
44 struct tps23881_priv {
45 struct i2c_client *client;
46 struct pse_controller_dev pcdev;
47 struct device_node *np;
48 struct tps23881_port_desc port[TPS23881_MAX_CHANS];
49 };
50
to_tps23881_priv(struct pse_controller_dev * pcdev)51 static struct tps23881_priv *to_tps23881_priv(struct pse_controller_dev *pcdev)
52 {
53 return container_of(pcdev, struct tps23881_priv, pcdev);
54 }
55
tps23881_pi_enable(struct pse_controller_dev * pcdev,int id)56 static int tps23881_pi_enable(struct pse_controller_dev *pcdev, int id)
57 {
58 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
59 struct i2c_client *client = priv->client;
60 u8 chan;
61 u16 val;
62 int ret;
63
64 if (id >= TPS23881_MAX_CHANS)
65 return -ERANGE;
66
67 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
68 if (ret < 0)
69 return ret;
70
71 chan = priv->port[id].chan[0];
72 if (chan < 4)
73 val = (u16)(ret | BIT(chan));
74 else
75 val = (u16)(ret | BIT(chan + 4));
76
77 if (priv->port[id].is_4p) {
78 chan = priv->port[id].chan[1];
79 if (chan < 4)
80 val |= BIT(chan);
81 else
82 val |= BIT(chan + 4);
83 }
84
85 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val);
86 if (ret)
87 return ret;
88
89 return 0;
90 }
91
tps23881_pi_disable(struct pse_controller_dev * pcdev,int id)92 static int tps23881_pi_disable(struct pse_controller_dev *pcdev, int id)
93 {
94 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
95 struct i2c_client *client = priv->client;
96 u8 chan;
97 u16 val;
98 int ret;
99
100 if (id >= TPS23881_MAX_CHANS)
101 return -ERANGE;
102
103 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
104 if (ret < 0)
105 return ret;
106
107 chan = priv->port[id].chan[0];
108 if (chan < 4)
109 val = (u16)(ret | BIT(chan + 4));
110 else
111 val = (u16)(ret | BIT(chan + 8));
112
113 if (priv->port[id].is_4p) {
114 chan = priv->port[id].chan[1];
115 if (chan < 4)
116 val |= BIT(chan + 4);
117 else
118 val |= BIT(chan + 8);
119 }
120
121 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PW_EN, val);
122 if (ret)
123 return ret;
124
125 return 0;
126 }
127
tps23881_pi_is_enabled(struct pse_controller_dev * pcdev,int id)128 static int tps23881_pi_is_enabled(struct pse_controller_dev *pcdev, int id)
129 {
130 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
131 struct i2c_client *client = priv->client;
132 bool enabled;
133 u8 chan;
134 int ret;
135
136 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
137 if (ret < 0)
138 return ret;
139
140 chan = priv->port[id].chan[0];
141 if (chan < 4)
142 enabled = ret & BIT(chan);
143 else
144 enabled = ret & BIT(chan + 4);
145
146 if (priv->port[id].is_4p) {
147 chan = priv->port[id].chan[1];
148 if (chan < 4)
149 enabled &= !!(ret & BIT(chan));
150 else
151 enabled &= !!(ret & BIT(chan + 4));
152 }
153
154 /* Return enabled status only if both channel are on this state */
155 return enabled;
156 }
157
tps23881_ethtool_get_status(struct pse_controller_dev * pcdev,unsigned long id,struct netlink_ext_ack * extack,struct pse_control_status * status)158 static int tps23881_ethtool_get_status(struct pse_controller_dev *pcdev,
159 unsigned long id,
160 struct netlink_ext_ack *extack,
161 struct pse_control_status *status)
162 {
163 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
164 struct i2c_client *client = priv->client;
165 bool enabled, delivering;
166 u8 chan;
167 int ret;
168
169 ret = i2c_smbus_read_word_data(client, TPS23881_REG_PW_STATUS);
170 if (ret < 0)
171 return ret;
172
173 chan = priv->port[id].chan[0];
174 if (chan < 4) {
175 enabled = ret & BIT(chan);
176 delivering = ret & BIT(chan + 4);
177 } else {
178 enabled = ret & BIT(chan + 4);
179 delivering = ret & BIT(chan + 8);
180 }
181
182 if (priv->port[id].is_4p) {
183 chan = priv->port[id].chan[1];
184 if (chan < 4) {
185 enabled &= !!(ret & BIT(chan));
186 delivering &= !!(ret & BIT(chan + 4));
187 } else {
188 enabled &= !!(ret & BIT(chan + 4));
189 delivering &= !!(ret & BIT(chan + 8));
190 }
191 }
192
193 /* Return delivering status only if both channel are on this state */
194 if (delivering)
195 status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
196 else
197 status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
198
199 /* Return enabled status only if both channel are on this state */
200 if (enabled)
201 status->c33_admin_state = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
202 else
203 status->c33_admin_state = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
204
205 return 0;
206 }
207
208 /* Parse managers subnode into a array of device node */
209 static int
tps23881_get_of_channels(struct tps23881_priv * priv,struct device_node * chan_node[TPS23881_MAX_CHANS])210 tps23881_get_of_channels(struct tps23881_priv *priv,
211 struct device_node *chan_node[TPS23881_MAX_CHANS])
212 {
213 struct device_node *channels_node, *node;
214 int i, ret;
215
216 if (!priv->np)
217 return -EINVAL;
218
219 channels_node = of_find_node_by_name(priv->np, "channels");
220 if (!channels_node)
221 return -EINVAL;
222
223 for_each_child_of_node(channels_node, node) {
224 u32 chan_id;
225
226 if (!of_node_name_eq(node, "channel"))
227 continue;
228
229 ret = of_property_read_u32(node, "reg", &chan_id);
230 if (ret) {
231 ret = -EINVAL;
232 goto out;
233 }
234
235 if (chan_id >= TPS23881_MAX_CHANS || chan_node[chan_id]) {
236 dev_err(&priv->client->dev,
237 "wrong number of port (%d)\n", chan_id);
238 ret = -EINVAL;
239 goto out;
240 }
241
242 of_node_get(node);
243 chan_node[chan_id] = node;
244 }
245
246 of_node_put(channels_node);
247 return 0;
248
249 out:
250 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
251 of_node_put(chan_node[i]);
252 chan_node[i] = NULL;
253 }
254
255 of_node_put(node);
256 of_node_put(channels_node);
257 return ret;
258 }
259
260 struct tps23881_port_matrix {
261 u8 pi_id;
262 u8 lgcl_chan[2];
263 u8 hw_chan[2];
264 bool is_4p;
265 bool exist;
266 };
267
268 static int
tps23881_match_channel(const struct pse_pi_pairset * pairset,struct device_node * chan_node[TPS23881_MAX_CHANS])269 tps23881_match_channel(const struct pse_pi_pairset *pairset,
270 struct device_node *chan_node[TPS23881_MAX_CHANS])
271 {
272 int i;
273
274 /* Look on every channels */
275 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
276 if (pairset->np == chan_node[i])
277 return i;
278 }
279
280 return -ENODEV;
281 }
282
283 static bool
tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int chan)284 tps23881_is_chan_free(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
285 int chan)
286 {
287 int i;
288
289 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
290 if (port_matrix[i].exist &&
291 (port_matrix[i].hw_chan[0] == chan ||
292 port_matrix[i].hw_chan[1] == chan))
293 return false;
294 }
295
296 return true;
297 }
298
299 /* Fill port matrix with the matching channels */
300 static int
tps23881_match_port_matrix(struct pse_pi * pi,int pi_id,struct device_node * chan_node[TPS23881_MAX_CHANS],struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])301 tps23881_match_port_matrix(struct pse_pi *pi, int pi_id,
302 struct device_node *chan_node[TPS23881_MAX_CHANS],
303 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
304 {
305 int ret;
306
307 if (!pi->pairset[0].np)
308 return 0;
309
310 ret = tps23881_match_channel(&pi->pairset[0], chan_node);
311 if (ret < 0)
312 return ret;
313
314 if (!tps23881_is_chan_free(port_matrix, ret)) {
315 pr_err("tps23881: channel %d already used\n", ret);
316 return -ENODEV;
317 }
318
319 port_matrix[pi_id].hw_chan[0] = ret;
320 port_matrix[pi_id].exist = true;
321
322 if (!pi->pairset[1].np)
323 return 0;
324
325 ret = tps23881_match_channel(&pi->pairset[1], chan_node);
326 if (ret < 0)
327 return ret;
328
329 if (!tps23881_is_chan_free(port_matrix, ret)) {
330 pr_err("tps23881: channel %d already used\n", ret);
331 return -ENODEV;
332 }
333
334 if (port_matrix[pi_id].hw_chan[0] / 4 != ret / 4) {
335 pr_err("tps23881: 4-pair PSE can only be set within the same 4 ports group");
336 return -ENODEV;
337 }
338
339 port_matrix[pi_id].hw_chan[1] = ret;
340 port_matrix[pi_id].is_4p = true;
341
342 return 0;
343 }
344
345 static int
tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int port_cnt)346 tps23881_get_unused_chan(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
347 int port_cnt)
348 {
349 bool used;
350 int i, j;
351
352 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
353 used = false;
354
355 for (j = 0; j < port_cnt; j++) {
356 if (port_matrix[j].hw_chan[0] == i) {
357 used = true;
358 break;
359 }
360
361 if (port_matrix[j].is_4p &&
362 port_matrix[j].hw_chan[1] == i) {
363 used = true;
364 break;
365 }
366 }
367
368 if (!used)
369 return i;
370 }
371
372 return -ENODEV;
373 }
374
375 /* Sort the port matrix to following particular hardware ports matrix
376 * specification of the tps23881. The device has two 4-ports groups and
377 * each 4-pair powered device has to be configured to use two consecutive
378 * logical channel in each 4 ports group (1 and 2 or 3 and 4). Also the
379 * hardware matrix has to be fully configured even with unused chan to be
380 * valid.
381 */
382 static int
tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])383 tps23881_sort_port_matrix(struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
384 {
385 struct tps23881_port_matrix tmp_port_matrix[TPS23881_MAX_CHANS] = {0};
386 int i, ret, port_cnt = 0, cnt_4ch_grp1 = 0, cnt_4ch_grp2 = 4;
387
388 /* Configure 4p port matrix */
389 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
390 int *cnt;
391
392 if (!port_matrix[i].exist || !port_matrix[i].is_4p)
393 continue;
394
395 if (port_matrix[i].hw_chan[0] < 4)
396 cnt = &cnt_4ch_grp1;
397 else
398 cnt = &cnt_4ch_grp2;
399
400 tmp_port_matrix[port_cnt].exist = true;
401 tmp_port_matrix[port_cnt].is_4p = true;
402 tmp_port_matrix[port_cnt].pi_id = i;
403 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0];
404 tmp_port_matrix[port_cnt].hw_chan[1] = port_matrix[i].hw_chan[1];
405
406 /* 4-pair ports have to be configured with consecutive
407 * logical channels 0 and 1, 2 and 3.
408 */
409 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++;
410 tmp_port_matrix[port_cnt].lgcl_chan[1] = (*cnt)++;
411
412 port_cnt++;
413 }
414
415 /* Configure 2p port matrix */
416 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
417 int *cnt;
418
419 if (!port_matrix[i].exist || port_matrix[i].is_4p)
420 continue;
421
422 if (port_matrix[i].hw_chan[0] < 4)
423 cnt = &cnt_4ch_grp1;
424 else
425 cnt = &cnt_4ch_grp2;
426
427 tmp_port_matrix[port_cnt].exist = true;
428 tmp_port_matrix[port_cnt].pi_id = i;
429 tmp_port_matrix[port_cnt].lgcl_chan[0] = (*cnt)++;
430 tmp_port_matrix[port_cnt].hw_chan[0] = port_matrix[i].hw_chan[0];
431
432 port_cnt++;
433 }
434
435 /* Complete the rest of the first 4 port group matrix even if
436 * channels are unused
437 */
438 while (cnt_4ch_grp1 < 4) {
439 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt);
440 if (ret < 0) {
441 pr_err("tps23881: port matrix issue, no chan available\n");
442 return ret;
443 }
444
445 if (port_cnt >= TPS23881_MAX_CHANS) {
446 pr_err("tps23881: wrong number of channels\n");
447 return -ENODEV;
448 }
449 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp1;
450 tmp_port_matrix[port_cnt].hw_chan[0] = ret;
451 cnt_4ch_grp1++;
452 port_cnt++;
453 }
454
455 /* Complete the rest of the second 4 port group matrix even if
456 * channels are unused
457 */
458 while (cnt_4ch_grp2 < 8) {
459 ret = tps23881_get_unused_chan(tmp_port_matrix, port_cnt);
460 if (ret < 0) {
461 pr_err("tps23881: port matrix issue, no chan available\n");
462 return -ENODEV;
463 }
464
465 if (port_cnt >= TPS23881_MAX_CHANS) {
466 pr_err("tps23881: wrong number of channels\n");
467 return -ENODEV;
468 }
469 tmp_port_matrix[port_cnt].lgcl_chan[0] = cnt_4ch_grp2;
470 tmp_port_matrix[port_cnt].hw_chan[0] = ret;
471 cnt_4ch_grp2++;
472 port_cnt++;
473 }
474
475 memcpy(port_matrix, tmp_port_matrix, sizeof(tmp_port_matrix));
476
477 return port_cnt;
478 }
479
480 /* Write port matrix to the hardware port matrix and the software port
481 * matrix.
482 */
483 static int
tps23881_write_port_matrix(struct tps23881_priv * priv,struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],int port_cnt)484 tps23881_write_port_matrix(struct tps23881_priv *priv,
485 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS],
486 int port_cnt)
487 {
488 struct i2c_client *client = priv->client;
489 u8 pi_id, lgcl_chan, hw_chan;
490 u16 val = 0;
491 int i, ret;
492
493 for (i = 0; i < port_cnt; i++) {
494 pi_id = port_matrix[i].pi_id;
495 lgcl_chan = port_matrix[i].lgcl_chan[0];
496 hw_chan = port_matrix[i].hw_chan[0] % 4;
497
498 /* Set software port matrix for existing ports */
499 if (port_matrix[i].exist)
500 priv->port[pi_id].chan[0] = lgcl_chan;
501
502 /* Set hardware port matrix for all ports */
503 val |= hw_chan << (lgcl_chan * 2);
504
505 if (!port_matrix[i].is_4p)
506 continue;
507
508 lgcl_chan = port_matrix[i].lgcl_chan[1];
509 hw_chan = port_matrix[i].hw_chan[1] % 4;
510
511 /* Set software port matrix for existing ports */
512 if (port_matrix[i].exist) {
513 priv->port[pi_id].is_4p = true;
514 priv->port[pi_id].chan[1] = lgcl_chan;
515 }
516
517 /* Set hardware port matrix for all ports */
518 val |= hw_chan << (lgcl_chan * 2);
519 }
520
521 /* Write hardware ports matrix */
522 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_MAP, val);
523 if (ret)
524 return ret;
525
526 return 0;
527 }
528
529 static int
tps23881_set_ports_conf(struct tps23881_priv * priv,struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])530 tps23881_set_ports_conf(struct tps23881_priv *priv,
531 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS])
532 {
533 struct i2c_client *client = priv->client;
534 int i, ret;
535 u16 val;
536
537 /* Set operating mode */
538 ret = i2c_smbus_write_word_data(client, TPS23881_REG_OP_MODE,
539 TPS23881_OP_MODE_SEMIAUTO);
540 if (ret)
541 return ret;
542
543 /* Disable DC disconnect */
544 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DIS_EN, 0x0);
545 if (ret)
546 return ret;
547
548 /* Set port power allocation */
549 val = 0;
550 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
551 if (!port_matrix[i].exist)
552 continue;
553
554 if (port_matrix[i].is_4p)
555 val |= 0xf << ((port_matrix[i].lgcl_chan[0] / 2) * 4);
556 else
557 val |= 0x3 << ((port_matrix[i].lgcl_chan[0] / 2) * 4);
558 }
559 ret = i2c_smbus_write_word_data(client, TPS23881_REG_PORT_POWER, val);
560 if (ret)
561 return ret;
562
563 /* Enable detection and classification */
564 val = 0;
565 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
566 if (!port_matrix[i].exist)
567 continue;
568
569 val |= BIT(port_matrix[i].lgcl_chan[0]) |
570 BIT(port_matrix[i].lgcl_chan[0] + 4);
571 if (port_matrix[i].is_4p)
572 val |= BIT(port_matrix[i].lgcl_chan[1]) |
573 BIT(port_matrix[i].lgcl_chan[1] + 4);
574 }
575 ret = i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN, val);
576 if (ret)
577 return ret;
578
579 return 0;
580 }
581
582 static int
tps23881_set_ports_matrix(struct tps23881_priv * priv,struct device_node * chan_node[TPS23881_MAX_CHANS])583 tps23881_set_ports_matrix(struct tps23881_priv *priv,
584 struct device_node *chan_node[TPS23881_MAX_CHANS])
585 {
586 struct tps23881_port_matrix port_matrix[TPS23881_MAX_CHANS] = {0};
587 int i, ret;
588
589 /* Update with values for every PSE PIs */
590 for (i = 0; i < TPS23881_MAX_CHANS; i++) {
591 ret = tps23881_match_port_matrix(&priv->pcdev.pi[i], i,
592 chan_node, port_matrix);
593 if (ret)
594 return ret;
595 }
596
597 ret = tps23881_sort_port_matrix(port_matrix);
598 if (ret < 0)
599 return ret;
600
601 ret = tps23881_write_port_matrix(priv, port_matrix, ret);
602 if (ret)
603 return ret;
604
605 ret = tps23881_set_ports_conf(priv, port_matrix);
606 if (ret)
607 return ret;
608
609 return 0;
610 }
611
tps23881_setup_pi_matrix(struct pse_controller_dev * pcdev)612 static int tps23881_setup_pi_matrix(struct pse_controller_dev *pcdev)
613 {
614 struct device_node *chan_node[TPS23881_MAX_CHANS] = {NULL};
615 struct tps23881_priv *priv = to_tps23881_priv(pcdev);
616 int ret, i;
617
618 ret = tps23881_get_of_channels(priv, chan_node);
619 if (ret < 0) {
620 dev_warn(&priv->client->dev,
621 "Unable to parse port-matrix, default matrix will be used\n");
622 return 0;
623 }
624
625 ret = tps23881_set_ports_matrix(priv, chan_node);
626
627 for (i = 0; i < TPS23881_MAX_CHANS; i++)
628 of_node_put(chan_node[i]);
629
630 return ret;
631 }
632
633 static const struct pse_controller_ops tps23881_ops = {
634 .setup_pi_matrix = tps23881_setup_pi_matrix,
635 .pi_enable = tps23881_pi_enable,
636 .pi_disable = tps23881_pi_disable,
637 .pi_is_enabled = tps23881_pi_is_enabled,
638 .ethtool_get_status = tps23881_ethtool_get_status,
639 };
640
641 static const char fw_parity_name[] = "ti/tps23881/tps23881-parity-14.bin";
642 static const char fw_sram_name[] = "ti/tps23881/tps23881-sram-14.bin";
643
644 struct tps23881_fw_conf {
645 u8 reg;
646 u8 val;
647 };
648
649 static const struct tps23881_fw_conf tps23881_fw_parity_conf[] = {
650 {.reg = 0x60, .val = 0x01},
651 {.reg = 0x62, .val = 0x00},
652 {.reg = 0x63, .val = 0x80},
653 {.reg = 0x60, .val = 0xC4},
654 {.reg = 0x1D, .val = 0xBC},
655 {.reg = 0xD7, .val = 0x02},
656 {.reg = 0x91, .val = 0x00},
657 {.reg = 0x90, .val = 0x00},
658 {.reg = 0xD7, .val = 0x00},
659 {.reg = 0x1D, .val = 0x00},
660 { /* sentinel */ }
661 };
662
663 static const struct tps23881_fw_conf tps23881_fw_sram_conf[] = {
664 {.reg = 0x60, .val = 0xC5},
665 {.reg = 0x62, .val = 0x00},
666 {.reg = 0x63, .val = 0x80},
667 {.reg = 0x60, .val = 0xC0},
668 {.reg = 0x1D, .val = 0xBC},
669 {.reg = 0xD7, .val = 0x02},
670 {.reg = 0x91, .val = 0x00},
671 {.reg = 0x90, .val = 0x00},
672 {.reg = 0xD7, .val = 0x00},
673 {.reg = 0x1D, .val = 0x00},
674 { /* sentinel */ }
675 };
676
tps23881_flash_sram_fw_part(struct i2c_client * client,const char * fw_name,const struct tps23881_fw_conf * fw_conf)677 static int tps23881_flash_sram_fw_part(struct i2c_client *client,
678 const char *fw_name,
679 const struct tps23881_fw_conf *fw_conf)
680 {
681 const struct firmware *fw = NULL;
682 int i, ret;
683
684 ret = request_firmware(&fw, fw_name, &client->dev);
685 if (ret)
686 return ret;
687
688 dev_dbg(&client->dev, "Flashing %s\n", fw_name);
689
690 /* Prepare device for RAM download */
691 while (fw_conf->reg) {
692 ret = i2c_smbus_write_byte_data(client, fw_conf->reg,
693 fw_conf->val);
694 if (ret)
695 goto out;
696
697 fw_conf++;
698 }
699
700 /* Flash the firmware file */
701 for (i = 0; i < fw->size; i++) {
702 ret = i2c_smbus_write_byte_data(client,
703 TPS23881_REG_SRAM_DATA,
704 fw->data[i]);
705 if (ret)
706 goto out;
707 }
708
709 out:
710 release_firmware(fw);
711 return ret;
712 }
713
tps23881_flash_sram_fw(struct i2c_client * client)714 static int tps23881_flash_sram_fw(struct i2c_client *client)
715 {
716 int ret;
717
718 ret = tps23881_flash_sram_fw_part(client, fw_parity_name,
719 tps23881_fw_parity_conf);
720 if (ret)
721 return ret;
722
723 ret = tps23881_flash_sram_fw_part(client, fw_sram_name,
724 tps23881_fw_sram_conf);
725 if (ret)
726 return ret;
727
728 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_SRAM_CTRL, 0x18);
729 if (ret)
730 return ret;
731
732 mdelay(12);
733
734 return 0;
735 }
736
tps23881_i2c_probe(struct i2c_client * client)737 static int tps23881_i2c_probe(struct i2c_client *client)
738 {
739 struct device *dev = &client->dev;
740 struct tps23881_priv *priv;
741 struct gpio_desc *reset;
742 int ret;
743 u8 val;
744
745 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
746 dev_err(dev, "i2c check functionality failed\n");
747 return -ENXIO;
748 }
749
750 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
751 if (!priv)
752 return -ENOMEM;
753
754 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
755 if (IS_ERR(reset))
756 return dev_err_probe(&client->dev, PTR_ERR(reset), "Failed to get reset GPIO\n");
757
758 if (reset) {
759 /* TPS23880 datasheet (Rev G) indicates minimum reset pulse is 5us */
760 usleep_range(5, 10);
761 gpiod_set_value_cansleep(reset, 0); /* De-assert reset */
762
763 /* TPS23880 datasheet indicates the minimum time after power on reset
764 * should be 20ms, but the document describing how to load SRAM ("How
765 * to Load TPS2388x SRAM and Parity Code over I2C" (Rev E))
766 * indicates we should delay that programming by at least 50ms. So
767 * we'll wait the entire 50ms here to ensure we're safe to go to the
768 * SRAM loading proceedure.
769 */
770 msleep(50);
771 }
772
773 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_DEVID);
774 if (ret < 0)
775 return ret;
776
777 if (FIELD_GET(TPS23881_REG_DEVID_MASK, ret) != TPS23881_DEVICE_ID) {
778 dev_err(dev, "Wrong device ID\n");
779 return -ENXIO;
780 }
781
782 ret = tps23881_flash_sram_fw(client);
783 if (ret < 0)
784 return ret;
785
786 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_FWREV);
787 if (ret < 0)
788 return ret;
789
790 dev_info(&client->dev, "Firmware revision 0x%x\n", ret);
791
792 /* Set configuration B, 16 bit access on a single device address */
793 ret = i2c_smbus_read_byte_data(client, TPS23881_REG_GEN_MASK);
794 if (ret < 0)
795 return ret;
796
797 val = ret | TPS23881_REG_NBITACC;
798 ret = i2c_smbus_write_byte_data(client, TPS23881_REG_GEN_MASK, val);
799 if (ret)
800 return ret;
801
802 priv->client = client;
803 i2c_set_clientdata(client, priv);
804 priv->np = dev->of_node;
805
806 priv->pcdev.owner = THIS_MODULE;
807 priv->pcdev.ops = &tps23881_ops;
808 priv->pcdev.dev = dev;
809 priv->pcdev.types = ETHTOOL_PSE_C33;
810 priv->pcdev.nr_lines = TPS23881_MAX_CHANS;
811 ret = devm_pse_controller_register(dev, &priv->pcdev);
812 if (ret) {
813 return dev_err_probe(dev, ret,
814 "failed to register PSE controller\n");
815 }
816
817 return ret;
818 }
819
820 static const struct i2c_device_id tps23881_id[] = {
821 { "tps23881" },
822 { }
823 };
824 MODULE_DEVICE_TABLE(i2c, tps23881_id);
825
826 static const struct of_device_id tps23881_of_match[] = {
827 { .compatible = "ti,tps23881", },
828 { },
829 };
830 MODULE_DEVICE_TABLE(of, tps23881_of_match);
831
832 static struct i2c_driver tps23881_driver = {
833 .probe = tps23881_i2c_probe,
834 .id_table = tps23881_id,
835 .driver = {
836 .name = "tps23881",
837 .of_match_table = tps23881_of_match,
838 },
839 };
840 module_i2c_driver(tps23881_driver);
841
842 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>");
843 MODULE_DESCRIPTION("TI TPS23881 PoE PSE Controller driver");
844 MODULE_LICENSE("GPL");
845