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Searched refs:TLBTEMP_BASE_2 (Results 1 – 2 of 2) sorted by relevance

/linux/Documentation/arch/xtensa/
H A Dmmu.rst89 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
132 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
176 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
/linux/arch/xtensa/include/asm/
H A Dpgtable.h71 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) macro