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Searched refs:TLBTEMP_BASE_1 (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/arch/xtensa/
H A Dmmu.rst86 | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE
129 | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE
173 | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE
/linux/arch/xtensa/mm/
H A Dhighmem.c57 BUILD_BUG_ON(PKMAP_BASE < TLBTEMP_BASE_1 + TLBTEMP_SIZE); in kmap_init()
H A Dmmu.c57 BUILD_BUG_ON(FIXADDR_START < TLBTEMP_BASE_1 + TLBTEMP_SIZE); in fixedrange_init()
/linux/arch/xtensa/include/asm/
H A Dpgtable.h70 #define TLBTEMP_BASE_1 (VMALLOC_START + 0x08000000) macro
71 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
/linux/arch/xtensa/kernel/
H A Dentry.S1753 movi a3, TLBTEMP_BASE_1