xref: /linux/drivers/net/wireless/realtek/rtw89/reg.h (revision 9410645520e9b820069761f3450ef6661418e279)
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_REG_H__
6 #define __RTW89_REG_H__
7 
8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
9 #define B_AX_AUTOLOAD_SUS BIT(5)
10 
11 #define R_AX_SYS_ISO_CTRL 0x0000
12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
16 
17 #define R_AX_SYS_FUNC_EN 0x0002
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
20 
21 #define R_AX_SYS_PW_CTRL 0x0004
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
24 #define B_AX_XTAL_OFF_A_DIE BIT(22)
25 #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
26 #define B_AX_RDY_SYSPWR BIT(17)
27 #define B_AX_EN_WLON BIT(16)
28 #define B_AX_APDM_HPDN BIT(15)
29 #define B_AX_PSUS_OFF_CAPC_EN BIT(14)
30 #define B_AX_AFSM_PCIE_SUS_EN BIT(12)
31 #define B_AX_AFSM_WLSUS_EN BIT(11)
32 #define B_AX_APFM_SWLPS BIT(10)
33 #define B_AX_APFM_OFFMAC BIT(9)
34 #define B_AX_APFN_ONMAC BIT(8)
35 
36 #define R_AX_SYS_CLK_CTRL 0x0008
37 #define B_AX_CPU_CLK_EN BIT(14)
38 
39 #define R_AX_SYS_SWR_CTRL1 0x0010
40 #define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10)
41 
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
43 #define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
44 #define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
45 
46 #define R_AX_RSV_CTRL 0x001C
47 #define B_AX_R_DIS_PRST BIT(6)
48 #define B_AX_WLOCK_1C_BIT6 BIT(5)
49 
50 #define R_AX_AFE_LDO_CTRL 0x0020
51 #define B_AX_AON_OFF_PC_EN BIT(23)
52 
53 #define R_AX_EFUSE_CTRL_1 0x0038
54 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
55 #define B_AX_EF_RDT BIT(27)
56 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
57 #define B_AX_EF_PGTS_MASK GENMASK(23, 20)
58 #define B_AX_EF_PD_DIS BIT(11)
59 #define B_AX_EF_POR BIT(10)
60 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
61 
62 #define R_AX_EFUSE_CTRL 0x0030
63 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
64 #define B_AX_EF_RDY BIT(29)
65 #define B_AX_EF_COMP_RESULT BIT(28)
66 #define B_AX_EF_ADDR_MASK GENMASK(26, 16)
67 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
68 
69 #define R_AX_EFUSE_CTRL_1_V1 0x0038
70 #define B_AX_EF_ENT BIT(31)
71 #define B_AX_EF_BURST BIT(19)
72 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
73 #define B_AX_EF_TROW_EN BIT(15)
74 #define B_AX_EF_ERR_FLAG BIT(14)
75 #define B_AX_EF_DSB_EN BIT(11)
76 #define B_AX_PCIE_CALIB_EN_V1 BIT(12)
77 #define B_AX_WDT_WAKE_PCIE_EN BIT(10)
78 #define B_AX_WDT_WAKE_USB_EN BIT(9)
79 
80 #define R_AX_GPIO_MUXCFG 0x0040
81 #define B_AX_BOOT_MODE BIT(19)
82 #define B_AX_WL_EECS_EXT_32K_SEL BIT(18)
83 #define B_AX_WL_SEC_BONDING_OPT_STS BIT(17)
84 #define B_AX_SECSIC_SEL BIT(16)
85 #define B_AX_ENHTP BIT(14)
86 #define B_AX_BT_AOD_GPIO3 BIT(13)
87 #define B_AX_ENSIC BIT(12)
88 #define B_AX_SIC_SWRST BIT(11)
89 #define B_AX_PO_WIFI_PTA_PINS BIT(10)
90 #define B_AX_PO_BT_PTA_PINS BIT(9)
91 #define B_AX_ENUARTTX BIT(8)
92 #define B_AX_BTMODE_MASK GENMASK(7, 6)
93 #define MAC_AX_BT_MODE_0_3 0
94 #define MAC_AX_BT_MODE_2 2
95 #define MAC_AX_RTK_MODE 0
96 #define MAC_AX_CSR_MODE 1
97 #define B_AX_ENBT BIT(5)
98 #define B_AX_EROM_EN BIT(4)
99 #define B_AX_ENUARTRX BIT(2)
100 #define B_AX_GPIOSEL_MASK GENMASK(1, 0)
101 
102 #define R_AX_DBG_CTRL 0x0058
103 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
104 #define B_AX_DBG_SEL1_16BIT BIT(27)
105 #define B_AX_DBG_SEL1 GENMASK(23, 16)
106 #define B_AX_DBG_SEL0_4BIT GENMASK(15, 14)
107 #define B_AX_DBG_SEL0_16BIT BIT(11)
108 #define B_AX_DBG_SEL0 GENMASK(7, 0)
109 
110 #define R_AX_GPIO_EXT_CTRL 0x0060
111 #define B_AX_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
112 #define B_AX_GPIO_MOD_9 BIT(25)
113 #define B_AX_GPIO_IO_SEL_15_TO_8_MASK GENMASK(23, 16)
114 #define B_AX_GPIO_IO_SEL_9 BIT(17)
115 #define B_AX_GPIO_OUT_15_TO_8_MASK GENMASK(15, 8)
116 #define B_AX_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)
117 #define B_AX_GPIO_IN_9 BIT(1)
118 
119 #define R_AX_SYS_SDIO_CTRL 0x0070
120 #define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15)
121 #define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14)
122 #define B_AX_PCIE_FORCE_PWR_NGAT BIT(13)
123 #define B_AX_PCIE_CALIB_EN_V1 BIT(12)
124 #define B_AX_PCIE_AUXCLK_GATE BIT(11)
125 #define B_AX_LTE_MUX_CTRL_PATH BIT(26)
126 
127 #define R_AX_HCI_OPT_CTRL 0x0074
128 #define BIT_WAKE_CTRL_V1 BIT(23)
129 #define BIT_WAKE_CTRL BIT(5)
130 
131 #define R_AX_HCI_BG_CTRL 0x0078
132 #define B_AX_IBX_EN_VALUE BIT(15)
133 #define B_AX_IB_EN_VALUE BIT(14)
134 #define B_AX_FORCED_IB_EN BIT(4)
135 #define B_AX_EN_REGBG BIT(3)
136 #define B_AX_R_AX_BG_LPF BIT(2)
137 #define B_AX_R_AX_BG GENMASK(1, 0)
138 
139 #define R_AX_HCI_LDO_CTRL 0x007A
140 #define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
141 
142 #define R_AX_PLATFORM_ENABLE 0x0088
143 #define B_AX_AXIDMA_EN BIT(3)
144 #define B_AX_APB_WRAP_EN BIT(2)
145 #define B_AX_WCPU_EN BIT(1)
146 #define B_AX_PLATFORM_EN BIT(0)
147 
148 #define R_AX_WLLPS_CTRL 0x0090
149 #define B_AX_LPSOP_ASWRM BIT(17)
150 #define B_AX_LPSOP_DSWRM BIT(9)
151 #define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
152 #define SW_LPS_OPTION 0x0001A0B2
153 
154 #define R_AX_SCOREBOARD  0x00AC
155 #define B_AX_TOGGLE BIT(31)
156 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
157 #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
158 #define B_MAC_AX_BTGS1_NOTIFY BIT(0)
159 #define MAC_AX_NOTIFY_TP_MAJOR 0x81
160 #define MAC_AX_NOTIFY_PWR_MAJOR 0x80
161 
162 #define R_AX_DBG_PORT_SEL 0x00C0
163 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
164 
165 #define R_AX_PMC_DBG_CTRL2 0x00CC
166 #define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2)
167 
168 #define R_AX_PCIE_MIO_INTF 0x00E4
169 #define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)
170 #define B_AX_PCIE_MIO_BYIOREG BIT(13)
171 #define B_AX_PCIE_MIO_RE BIT(12)
172 #define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8)
173 #define MIO_WRITE_BYTE_ALL 0xF
174 #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
175 #define MIO_ADDR_PAGE_MASK GENMASK(12, 8)
176 
177 #define R_AX_PCIE_MIO_INTD 0x00E8
178 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
179 
180 #define R_AX_SYS_CFG1 0x00F0
181 #define B_AX_CHIP_VER_MASK GENMASK(15, 12)
182 
183 #define R_AX_SYS_STATUS1 0x00F4
184 #define B_AX_SEL_0XC0_MASK GENMASK(17, 16)
185 #define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)
186 #define MAC_AX_HCI_SEL_SDIO_UART 0
187 #define MAC_AX_HCI_SEL_MULTI_USB 1
188 #define MAC_AX_HCI_SEL_PCIE_UART 2
189 #define MAC_AX_HCI_SEL_PCIE_USB 3
190 #define MAC_AX_HCI_SEL_MULTI_SDIO 4
191 
192 #define R_AX_HALT_H2C_CTRL 0x0160
193 #define R_AX_HALT_H2C 0x0168
194 #define B_AX_HALT_H2C_TRIGGER BIT(0)
195 #define R_AX_HALT_C2H_CTRL 0x0164
196 #define R_AX_HALT_C2H 0x016C
197 
198 #define R_AX_WCPU_FW_CTRL 0x01E0
199 #define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)
200 #define B_AX_FWDL_PATH_RDY BIT(2)
201 #define B_AX_H2C_PATH_RDY BIT(1)
202 #define B_AX_WCPU_FWDL_EN BIT(0)
203 
204 #define R_AX_RPWM 0x01E4
205 #define R_AX_PCIE_HRPWM 0x10C0
206 #define PS_RPWM_TOGGLE BIT(15)
207 #define PS_RPWM_ACK BIT(14)
208 #define PS_RPWM_SEQ_NUM GENMASK(13, 12)
209 #define PS_RPWM_NOTIFY_WAKE BIT(8)
210 #define PS_RPWM_STATE 0x7
211 #define RPWM_SEQ_NUM_MAX 3
212 #define PS_CPWM_SEQ_NUM GENMASK(13, 12)
213 #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
214 #define PS_CPWM_STATE GENMASK(2, 0)
215 #define CPWM_SEQ_NUM_MAX 3
216 
217 #define R_AX_BOOT_REASON 0x01E6
218 #define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
219 
220 #define R_AX_LDM 0x01E8
221 #define B_AX_EN_32K BIT(31)
222 
223 #define R_AX_UDM0 0x01F0
224 #define R_AX_UDM1 0x01F4
225 #define B_AX_UDM1_MASK GENMASK(31, 16)
226 #define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)
227 #define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)
228 #define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
229 #define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
230 #define R_AX_UDM2 0x01F8
231 #define R_AX_UDM3 0x01FC
232 
233 #define R_AX_SPS_DIG_ON_CTRL0 0x0200
234 #define B_AX_VREFPFM_L_MASK GENMASK(25, 22)
235 #define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17)
236 #define B_AX_OCP_L1_MASK GENMASK(15, 13)
237 #define B_AX_VOL_L1_MASK GENMASK(3, 0)
238 
239 #define R_AX_SPSLDO_ON_CTRL1 0x0204
240 #define B_AX_FPWMDELAY BIT(3)
241 
242 #define R_AX_LDO_AON_CTRL0 0x0218
243 #define B_AX_PD_REGU_L BIT(16)
244 
245 #define R_AX_SPSANA_ON_CTRL1 0x0224
246 
247 #define R_AX_SPS_ANA_ON_CTRL2 0x0228
248 #define RTL8852B_RFE_05_SPS_ANA 0x4A82
249 
250 #define R_AX_WLAN_XTAL_SI_CTRL 0x0270
251 #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
252 #define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30)
253 #define B_AX_WL_XTAL_GNT BIT(29)
254 #define B_AX_BT_XTAL_GNT BIT(28)
255 #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
256 #define XTAL_SI_NORMAL_WRITE 0x00
257 #define XTAL_SI_NORMAL_READ 0x01
258 #define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
259 #define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
260 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
261 
262 #define R_AX_WLAN_XTAL_SI_CONFIG 0x0274
263 #define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0)
264 
265 #define R_AX_XTAL_ON_CTRL0 0x0280
266 #define B_AX_XTAL_SC_LPS BIT(31)
267 #define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
268 #define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)
269 #define B_AX_XTAL_SC_MASK GENMASK(6, 0)
270 
271 #define R_AX_XTAL_ON_CTRL3 0x028C
272 #define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24)
273 #define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16)
274 #define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8)
275 #define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0)
276 
277 #define R_AX_GPIO0_7_FUNC_SEL 0x02D0
278 
279 #define R_AX_GPIO8_15_FUNC_SEL 0x02D4
280 #define B_AX_PINMUX_GPIO9_FUNC_SEL_MASK GENMASK(7, 4)
281 
282 #define R_AX_EECS_EESK_FUNC_SEL 0x02D8
283 #define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
284 
285 #define R_AX_GPIO16_23_FUNC_SEL 0x02D8
286 #define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)
287 #define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0)
288 
289 #define R_AX_LED1_FUNC_SEL 0x02DC
290 #define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
291 #define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
292 
293 #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
294 #define B_AX_LED1_PULL_LOW_EN BIT(18)
295 #define B_AX_EESK_PULL_LOW_EN BIT(17)
296 #define B_AX_EECS_PULL_LOW_EN BIT(16)
297 
298 #define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
299 #define B_AX_GPIO16_PULL_LOW_EN_V1 BIT(19)
300 #define B_AX_GPIO10_PULL_LOW_EN BIT(10)
301 
302 #define R_AX_WLRF_CTRL 0x02F0
303 #define B_AX_AFC_AFEDIG BIT(17)
304 #define B_AX_WLRF1_CTRL_7 BIT(15)
305 #define B_AX_WLRF1_CTRL_1 BIT(9)
306 #define B_AX_WLRF_CTRL_7 BIT(7)
307 #define B_AX_WLRF_CTRL_1 BIT(1)
308 
309 #define R_AX_IC_PWR_STATE 0x03F0
310 #define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
311 #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
312 #define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
313 #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
314 #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
315 #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
316 
317 #define R_AX_SPS_DIG_OFF_CTRL0 0x0400
318 #define B_AX_C3_L1_MASK GENMASK(5, 4)
319 #define B_AX_C1_L1_MASK GENMASK(1, 0)
320 
321 #define R_AX_AFE_OFF_CTRL1 0x0444
322 #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
323 #define B_AX_S1_LDO2PWRCUT_F BIT(23)
324 #define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
325 
326 #define R_AX_DBG_WOW 0x0504
327 #define B_AX_DBG_WOW_CPU_IO_RX_EN BIT(8)
328 
329 #define R_AX_SEC_CTRL 0x0C00
330 #define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16)
331 
332 #define R_AX_FILTER_MODEL_ADDR 0x0C04
333 
334 #define R_AX_HAXI_INIT_CFG1 0x1000
335 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
336 #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
337 #define B_AX_DMA_MODE_MASK GENMASK(19, 18)
338 #define DMA_MOD_PCIE_1B 0x0
339 #define DMA_MOD_PCIE_4B 0x1
340 #define DMA_MOD_USB 0x2
341 #define DMA_MOD_SDIO 0x3
342 #define B_AX_STOP_AXI_MST BIT(17)
343 #define B_AX_HAXI_RST_KEEP_REG BIT(16)
344 #define B_AX_RXHCI_EN_V1 BIT(15)
345 #define B_AX_RXBD_MODE_V1 BIT(14)
346 #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
347 #define B_AX_TXHCI_EN_V1 BIT(7)
348 #define B_AX_FLUSH_AXI_MST BIT(4)
349 #define B_AX_RST_BDRAM BIT(3)
350 #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
351 
352 #define R_AX_HAXI_DMA_STOP1 0x1010
353 #define B_AX_STOP_WPDMA BIT(19)
354 #define B_AX_STOP_CH12 BIT(18)
355 #define B_AX_STOP_CH9 BIT(17)
356 #define B_AX_STOP_CH8 BIT(16)
357 #define B_AX_STOP_ACH7 BIT(15)
358 #define B_AX_STOP_ACH6 BIT(14)
359 #define B_AX_STOP_ACH5 BIT(13)
360 #define B_AX_STOP_ACH4 BIT(12)
361 #define B_AX_STOP_ACH3 BIT(11)
362 #define B_AX_STOP_ACH2 BIT(10)
363 #define B_AX_STOP_ACH1 BIT(9)
364 #define B_AX_STOP_ACH0 BIT(8)
365 
366 #define R_AX_HAXI_DMA_BUSY1 0x101C
367 #define B_AX_HAXIIO_BUSY BIT(20)
368 #define B_AX_WPDMA_BUSY BIT(19)
369 #define B_AX_CH12_BUSY BIT(18)
370 #define B_AX_CH9_BUSY BIT(17)
371 #define B_AX_CH8_BUSY BIT(16)
372 #define B_AX_ACH7_BUSY BIT(15)
373 #define B_AX_ACH6_BUSY BIT(14)
374 #define B_AX_ACH5_BUSY BIT(13)
375 #define B_AX_ACH4_BUSY BIT(12)
376 #define B_AX_ACH3_BUSY BIT(11)
377 #define B_AX_ACH2_BUSY BIT(10)
378 #define B_AX_ACH1_BUSY BIT(9)
379 #define B_AX_ACH0_BUSY BIT(8)
380 
381 #define R_AX_PCIE_DBG_CTRL 0x11C0
382 #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
383 #define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13)
384 #define B_AX_MRD_TIMEOUT_EN BIT(10)
385 #define B_AX_ASFF_FULL_NO_STK BIT(1)
386 #define B_AX_EN_STUCK_DBG BIT(0)
387 
388 #define R_AX_HAXI_DMA_STOP2 0x11C0
389 #define B_AX_STOP_CH11 BIT(1)
390 #define B_AX_STOP_CH10 BIT(0)
391 
392 #define R_AX_HAXI_DMA_BUSY2 0x11C8
393 #define B_AX_CH11_BUSY BIT(1)
394 #define B_AX_CH10_BUSY BIT(0)
395 
396 #define R_AX_HAXI_DMA_BUSY3 0x1208
397 #define B_AX_RPQ_BUSY BIT(1)
398 #define B_AX_RXQ_BUSY BIT(0)
399 
400 #define R_AX_LTR_DEC_CTRL 0x1600
401 #define B_AX_LTR_IDX_DRV_VLD BIT(16)
402 #define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)
403 #define B_AX_LTR_IDX_FW_VLD BIT(13)
404 #define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)
405 #define B_AX_LTR_IDX_HW_VLD BIT(10)
406 #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
407 #define B_AX_LTR_REQ_DRV BIT(7)
408 #define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)
409 #define PCIE_LTR_IDX_IDLE 3
410 #define B_AX_LTR_DRV_DEC_EN BIT(4)
411 #define B_AX_LTR_FW_DEC_EN BIT(3)
412 #define B_AX_LTR_HW_DEC_EN BIT(2)
413 #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
414 #define LTR_EN_BITS (B_AX_LTR_HW_DEC_EN | B_AX_LTR_FW_DEC_EN | B_AX_LTR_DRV_DEC_EN)
415 
416 #define R_AX_LTR_LATENCY_IDX0 0x1604
417 #define R_AX_LTR_LATENCY_IDX1 0x1608
418 #define R_AX_LTR_LATENCY_IDX2 0x160C
419 #define R_AX_LTR_LATENCY_IDX3 0x1610
420 
421 #define R_AX_HCI_FC_CTRL_V1 0x1700
422 #define R_AX_CH_PAGE_CTRL_V1 0x1704
423 
424 #define R_AX_ACH0_PAGE_CTRL_V1 0x1710
425 #define R_AX_ACH1_PAGE_CTRL_V1 0x1714
426 #define R_AX_ACH2_PAGE_CTRL_V1 0x1718
427 #define R_AX_ACH3_PAGE_CTRL_V1 0x171C
428 #define R_AX_ACH4_PAGE_CTRL_V1 0x1720
429 #define R_AX_ACH5_PAGE_CTRL_V1 0x1724
430 #define R_AX_ACH6_PAGE_CTRL_V1 0x1728
431 #define R_AX_ACH7_PAGE_CTRL_V1 0x172C
432 #define R_AX_CH8_PAGE_CTRL_V1 0x1730
433 #define R_AX_CH9_PAGE_CTRL_V1 0x1734
434 #define R_AX_CH10_PAGE_CTRL_V1 0x1738
435 #define R_AX_CH11_PAGE_CTRL_V1 0x173C
436 
437 #define R_AX_ACH0_PAGE_INFO_V1 0x1750
438 #define R_AX_ACH1_PAGE_INFO_V1 0x1754
439 #define R_AX_ACH2_PAGE_INFO_V1 0x1758
440 #define R_AX_ACH3_PAGE_INFO_V1 0x175C
441 #define R_AX_ACH4_PAGE_INFO_V1 0x1760
442 #define R_AX_ACH5_PAGE_INFO_V1 0x1764
443 #define R_AX_ACH6_PAGE_INFO_V1 0x1768
444 #define R_AX_ACH7_PAGE_INFO_V1 0x176C
445 #define R_AX_CH8_PAGE_INFO_V1 0x1770
446 #define R_AX_CH9_PAGE_INFO_V1 0x1774
447 #define R_AX_CH10_PAGE_INFO_V1 0x1778
448 #define R_AX_CH11_PAGE_INFO_V1 0x177C
449 #define R_AX_CH12_PAGE_INFO_V1 0x1780
450 
451 #define R_AX_PUB_PAGE_INFO3_V1 0x178C
452 #define R_AX_PUB_PAGE_CTRL1_V1 0x1790
453 #define R_AX_PUB_PAGE_CTRL2_V1 0x1794
454 #define R_AX_PUB_PAGE_INFO1_V1 0x1798
455 #define R_AX_PUB_PAGE_INFO2_V1 0x179C
456 #define R_AX_WP_PAGE_CTRL1_V1 0x17A0
457 #define R_AX_WP_PAGE_CTRL2_V1 0x17A4
458 #define R_AX_WP_PAGE_INFO1_V1 0x17A8
459 
460 #define R_AX_H2CREG_DATA0_V1 0x7140
461 #define R_AX_H2CREG_DATA1_V1 0x7144
462 #define R_AX_H2CREG_DATA2_V1 0x7148
463 #define R_AX_H2CREG_DATA3_V1 0x714C
464 #define R_AX_C2HREG_DATA0_V1 0x7150
465 #define R_AX_C2HREG_DATA1_V1 0x7154
466 #define R_AX_C2HREG_DATA2_V1 0x7158
467 #define R_AX_C2HREG_DATA3_V1 0x715C
468 #define R_AX_H2CREG_CTRL_V1 0x7160
469 #define R_AX_C2HREG_CTRL_V1 0x7164
470 
471 #define R_AX_HCI_FUNC_EN_V1 0x7880
472 
473 #define R_AX_PHYREG_SET 0x8040
474 #define PHYREG_SET_ALL_CYCLE 0x8
475 #define PHYREG_SET_XYN_CYCLE 0xE
476 
477 #define R_AX_HD0IMR 0x8110
478 #define B_AX_WDT_PTFM_INT_EN BIT(5)
479 #define B_AX_CPWM_INT_EN BIT(2)
480 #define B_AX_GT3_INT_EN BIT(1)
481 #define B_AX_C2H_INT_EN BIT(0)
482 #define R_AX_HD0ISR 0x8114
483 #define B_AX_C2H_INT BIT(0)
484 
485 #define R_AX_H2CREG_DATA0 0x8140
486 #define R_AX_H2CREG_DATA1 0x8144
487 #define R_AX_H2CREG_DATA2 0x8148
488 #define R_AX_H2CREG_DATA3 0x814C
489 #define R_AX_C2HREG_DATA0 0x8150
490 #define R_AX_C2HREG_DATA1 0x8154
491 #define R_AX_C2HREG_DATA2 0x8158
492 #define R_AX_C2HREG_DATA3 0x815C
493 #define R_AX_H2CREG_CTRL 0x8160
494 #define B_AX_H2CREG_TRIGGER BIT(0)
495 #define R_AX_C2HREG_CTRL 0x8164
496 #define B_AX_C2HREG_TRIGGER BIT(0)
497 #define R_AX_CPWM 0x8170
498 
499 #define R_AX_HCI_FUNC_EN 0x8380
500 #define B_AX_HCI_RXDMA_EN BIT(1)
501 #define B_AX_HCI_TXDMA_EN BIT(0)
502 
503 #define R_AX_BOOT_DBG 0x83F0
504 
505 #define R_AX_DMAC_FUNC_EN 0x8400
506 #define B_AX_DMAC_CRPRT BIT(31)
507 #define B_AX_MAC_FUNC_EN BIT(30)
508 #define B_AX_DMAC_FUNC_EN BIT(29)
509 #define B_AX_MPDU_PROC_EN BIT(28)
510 #define B_AX_WD_RLS_EN BIT(27)
511 #define B_AX_DLE_WDE_EN BIT(26)
512 #define B_AX_TXPKT_CTRL_EN BIT(25)
513 #define B_AX_STA_SCH_EN BIT(24)
514 #define B_AX_DLE_PLE_EN BIT(23)
515 #define B_AX_PKT_BUF_EN BIT(22)
516 #define B_AX_DMAC_TBL_EN BIT(21)
517 #define B_AX_PKT_IN_EN BIT(20)
518 #define B_AX_DLE_CPUIO_EN BIT(19)
519 #define B_AX_DISPATCHER_EN BIT(18)
520 #define B_AX_BBRPT_EN BIT(17)
521 #define B_AX_MAC_SEC_EN BIT(16)
522 #define B_AX_DMACREG_GCKEN BIT(15)
523 #define B_AX_MAC_UN_EN BIT(15)
524 #define B_AX_H_AXIDMA_EN BIT(14)
525 
526 #define R_AX_DMAC_CLK_EN 0x8404
527 #define B_AX_WD_RLS_CLK_EN BIT(27)
528 #define B_AX_DLE_WDE_CLK_EN BIT(26)
529 #define B_AX_TXPKT_CTRL_CLK_EN BIT(25)
530 #define B_AX_STA_SCH_CLK_EN BIT(24)
531 #define B_AX_DLE_PLE_CLK_EN BIT(23)
532 #define B_AX_PKT_IN_CLK_EN BIT(20)
533 #define B_AX_DLE_CPUIO_CLK_EN BIT(19)
534 #define B_AX_DISPATCHER_CLK_EN BIT(18)
535 #define B_AX_BBRPT_CLK_EN BIT(17)
536 #define B_AX_MAC_SEC_CLK_EN BIT(16)
537 #define B_AX_AXIDMA_CLK_EN BIT(9)
538 
539 #define PCI_LTR_IDLE_TIMER_1US 0
540 #define PCI_LTR_IDLE_TIMER_10US 1
541 #define PCI_LTR_IDLE_TIMER_100US 2
542 #define PCI_LTR_IDLE_TIMER_200US 3
543 #define PCI_LTR_IDLE_TIMER_400US 4
544 #define PCI_LTR_IDLE_TIMER_800US 5
545 #define PCI_LTR_IDLE_TIMER_1_6MS 6
546 #define PCI_LTR_IDLE_TIMER_3_2MS 7
547 #define PCI_LTR_IDLE_TIMER_R_ERR 0xFD
548 #define PCI_LTR_IDLE_TIMER_DEF 0xFE
549 #define PCI_LTR_IDLE_TIMER_IGNORE 0xFF
550 
551 #define PCI_LTR_SPC_10US 0
552 #define PCI_LTR_SPC_100US 1
553 #define PCI_LTR_SPC_500US 2
554 #define PCI_LTR_SPC_1MS 3
555 #define PCI_LTR_SPC_R_ERR 0xFD
556 #define PCI_LTR_SPC_DEF 0xFE
557 #define PCI_LTR_SPC_IGNORE 0xFF
558 
559 #define R_AX_LTR_CTRL_0 0x8410
560 #define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12)
561 #define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
562 #define B_AX_LTR_WD_NOEMP_CHK BIT(6)
563 #define B_AX_APP_LTR_ACT BIT(5)
564 #define B_AX_APP_LTR_IDLE BIT(4)
565 #define B_AX_LTR_EN BIT(1)
566 #define B_AX_LTR_WD_NOEMP_CHK_V1 BIT(1)
567 #define B_AX_LTR_HW_EN BIT(0)
568 
569 #define R_AX_LTR_CTRL_1 0x8414
570 #define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16)
571 #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
572 
573 #define R_AX_LTR_IDLE_LATENCY 0x8418
574 
575 #define R_AX_LTR_ACTIVE_LATENCY 0x841C
576 
577 #define R_AX_SER_DBG_INFO 0x8424
578 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
579 
580 #define R_AX_DLE_EMPTY0 0x8430
581 #define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26)
582 #define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25)
583 #define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
584 #define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23)
585 #define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22)
586 #define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21)
587 #define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20)
588 #define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19)
589 #define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18)
590 #define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17)
591 #define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16)
592 #define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10)
593 #define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
594 #define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8)
595 #define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7)
596 #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
597 #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3)
598 #define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2)
599 #define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
600 #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
601 
602 #define R_AX_DLE_EMPTY1 0x8434
603 #define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20)
604 #define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19)
605 #define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18)
606 #define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17)
607 #define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16)
608 #define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5)
609 #define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
610 #define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3)
611 #define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2)
612 #define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1)
613 #define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
614 
615 #define R_AX_DMAC_ERR_IMR 0x8520
616 #define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10)
617 #define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
618 #define B_AX_DISPATCH_ERR_INT_EN BIT(8)
619 #define B_AX_PKTIN_ERR_INT_EN BIT(7)
620 #define B_AX_PLE_DLE_ERR_INT_EN BIT(6)
621 #define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5)
622 #define B_AX_WDE_DLE_ERR_INT_EN BIT(4)
623 #define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3)
624 #define B_AX_MPDU_ERR_INT_EN BIT(2)
625 #define B_AX_WSEC_ERR_INT_EN BIT(1)
626 #define B_AX_WDRLS_ERR_INT_EN BIT(0)
627 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
628 #define DMAC_ERR_IMR_DIS 0
629 
630 #define R_AX_DMAC_ERR_ISR 0x8524
631 #define B_AX_HAXIDMA_ERR_FLAG BIT(14)
632 #define B_AX_PAXIDMA_ERR_FLAG BIT(13)
633 #define B_AX_HCI_BUF_ERR_FLAG BIT(12)
634 #define B_AX_BBRPT_ERR_FLAG BIT(11)
635 #define B_AX_DLE_CPUIO_ERR_FLAG BIT(10)
636 #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
637 #define B_AX_DISPATCH_ERR_FLAG BIT(8)
638 #define B_AX_PKTIN_ERR_FLAG BIT(7)
639 #define B_AX_PLE_DLE_ERR_FLAG BIT(6)
640 #define B_AX_TXPKTCTRL_ERR_FLAG BIT(5)
641 #define B_AX_WDE_DLE_ERR_FLAG BIT(4)
642 #define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3)
643 #define B_AX_MPDU_ERR_FLAG BIT(2)
644 #define B_AX_WSEC_ERR_FLAG BIT(1)
645 #define B_AX_WDRLS_ERR_FLAG BIT(0)
646 
647 #define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800
648 #define B_AX_PL_PAGE_128B_SEL BIT(9)
649 #define B_AX_WD_PAGE_64B_SEL BIT(8)
650 #define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804
651 #define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808
652 #define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C
653 #define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810
654 #define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0)
655 
656 #define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850
657 #define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
658 #define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30)
659 #define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29)
660 #define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
661 #define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27)
662 #define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26)
663 #define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25)
664 #define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24)
665 #define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21)
666 #define B_AX_HDT_RES_ERR_INT_EN BIT(20)
667 #define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19)
668 #define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18)
669 #define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17)
670 #define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16)
671 #define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15)
672 #define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14)
673 #define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13)
674 #define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12)
675 #define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11)
676 #define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10)
677 #define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9)
678 #define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8)
679 #define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7)
680 #define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
681 #define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5)
682 #define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4)
683 #define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3)
684 #define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2)
685 #define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1)
686 #define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0)
687 #define B_AX_HOST_DISP_IMR_CLR (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
688 				B_AX_HDT_CHANNEL_ID_ERR_INT_EN | \
689 				B_AX_HDT_PKT_FAIL_DBG_INT_EN | \
690 				B_AX_HDT_PERMU_OVERFLOW_INT_EN | \
691 				B_AX_HDT_PERMU_UNDERFLOW_INT_EN | \
692 				B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
693 				B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
694 				B_AX_HDT_OFFSET_UNMATCH_INT_EN | \
695 				B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
696 				B_AX_HDT_WD_CHK_ERR_INT_EN | \
697 				B_AX_HDT_PRE_COST_ERR_INT_EN | \
698 				B_AX_HDT_TXPKTSIZE_ERR_INT_EN | \
699 				B_AX_HDT_TCP_CHK_ERR_INT_EN | \
700 				B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN | \
701 				B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN | \
702 				B_AX_HDT_PLD_CMD_OVERLOW_INT_EN | \
703 				B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN | \
704 				B_AX_HDT_FLOW_CTRL_ERR_INT_EN | \
705 				B_AX_HDT_NULLPKT_ERR_INT_EN | \
706 				B_AX_HDT_BURST_NUM_ERR_INT_EN | \
707 				B_AX_HDT_RXAGG_CFG_ERR_INT_EN | \
708 				B_AX_HDT_SHIFT_EN_ERR_INT_EN | \
709 				B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
710 				B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \
711 				B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN | \
712 				B_AX_HDT_CHKSUM_FSM_ERR_INT_EN | \
713 				B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \
714 				B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN)
715 #define B_AX_HOST_DISP_IMR_SET (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
716 				B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
717 				B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
718 				B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
719 				B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
720 				B_AX_HDT_DMA_PROCESS_ERR_INT_EN)
721 #define B_AX_HOST_DISP_IMR_SET_V01 (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
722 				    B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
723 				    B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
724 				    B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
725 				    B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
726 				    B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \
727 				    B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \
728 				    B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN)
729 
730 #define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
731 #define B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30)
732 #define B_AX_HR_CHKSUM_FSM_ERR_INT_EN BIT(29)
733 #define B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
734 #define B_AX_HR_DMA_PROCESS_ERR_INT_EN BIT(27)
735 #define B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26)
736 #define B_AX_HR_SHIFT_EN_ERR_INT_EN BIT(25)
737 #define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24)
738 #define B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN BIT(23)
739 #define B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22)
740 #define B_AX_HT_ILL_CH_ERR_INT_EN BIT(20)
741 #define B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18)
742 #define B_AX_HT_WD_LEN_OVER_ERR_INT_EN BIT(17)
743 #define B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16)
744 #define B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15)
745 #define B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14)
746 #define B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13)
747 #define B_AX_HT_CHKSUM_FSM_ERR_INT_EN BIT(12)
748 #define B_AX_HT_TXPKTSIZE_ERR_INT_EN BIT(11)
749 #define B_AX_HT_PRE_SUB_ERR_INT_EN BIT(10)
750 #define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
751 #define B_AX_HT_CHANNEL_DMA_ERR_INT_EN BIT(8)
752 #define B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
753 #define B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
754 #define B_AX_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
755 #define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
756 #define B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
757 #define B_AX_HT_PKT_FAIL_ERR_INT_EN BIT(2)
758 #define B_AX_HT_CH_ID_ERR_INT_EN BIT(1)
759 #define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
760 #define B_AX_HOST_DISP_IMR_CLR_V1 (B_AX_HT_EP_CH_DIFF_ERR_INT_EN | \
761 				   B_AX_HT_CH_ID_ERR_INT_EN | \
762 				   B_AX_HT_PKT_FAIL_ERR_INT_EN | \
763 				   B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
764 				   B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
765 				   B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \
766 				   B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \
767 				   B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN | \
768 				   B_AX_HT_CHANNEL_DMA_ERR_INT_EN | \
769 				   B_AX_HT_WD_CHKSUM_ERR_INT_EN | \
770 				   B_AX_HT_PRE_SUB_ERR_INT_EN | \
771 				   B_AX_HT_TXPKTSIZE_ERR_INT_EN | \
772 				   B_AX_HT_CHKSUM_FSM_ERR_INT_EN | \
773 				   B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN | \
774 				   B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
775 				   B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
776 				   B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
777 				   B_AX_HT_WD_LEN_OVER_ERR_INT_EN | \
778 				   B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN | \
779 				   B_AX_HT_ILL_CH_ERR_INT_EN | \
780 				   B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN | \
781 				   B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN | \
782 				   B_AX_HR_AGG_CFG_ERR_INT_EN | \
783 				   B_AX_HR_SHIFT_EN_ERR_INT_EN | \
784 				   B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
785 				   B_AX_HR_DMA_PROCESS_ERR_INT_EN | \
786 				   B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN | \
787 				   B_AX_HR_CHKSUM_FSM_ERR_INT_EN | \
788 				   B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN | \
789 				   B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN)
790 #define B_AX_HOST_DISP_IMR_SET_V1 (B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \
791 				   B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \
792 				   B_AX_HT_ILL_CH_ERR_INT_EN | \
793 				   B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
794 				   B_AX_HR_DMA_PROCESS_ERR_INT_EN)
795 
796 #define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854
797 #define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
798 #define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30)
799 #define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29)
800 #define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
801 #define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27)
802 #define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26)
803 #define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25)
804 #define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24)
805 #define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20)
806 #define B_AX_CPU_RESP_ERR_INT_EN BIT(19)
807 #define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18)
808 #define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17)
809 #define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16)
810 #define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15)
811 #define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14)
812 #define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13)
813 #define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12)
814 #define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11)
815 #define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10)
816 #define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9)
817 #define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8)
818 #define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
819 #define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
820 #define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5)
821 #define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4)
822 #define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3)
823 #define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2)
824 #define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1)
825 #define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0)
826 #define B_AX_CPU_DISP_IMR_CLR (B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN | \
827 			       B_AX_CPU_PKT_FAIL_DBG_INT_EN | \
828 			       B_AX_CPU_CHANNEL_ID_ERR_INT_EN | \
829 			       B_AX_CPU_PERMU_OVERFLOW_INT_EN | \
830 			       B_AX_CPU_PERMU_UNDERFLOW_INT_EN | \
831 			       B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \
832 			       B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \
833 			       B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN | \
834 			       B_AX_CPU_OFFSET_UNMATCH_INT_EN | \
835 			       B_AX_CPU_CHANNEL_DMA_ERR_INT_EN | \
836 			       B_AX_CPU_WD_CHK_ERR_INT_EN | \
837 			       B_AX_CPU_PRE_COST_ERR_INT_EN | \
838 			       B_AX_CPU_PLD_CMD_OVERLOW_INT_EN | \
839 			       B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN | \
840 			       B_AX_CPU_F2P_QSEL_ERR_INT_EN | \
841 			       B_AX_CPU_F2P_SEQ_ERR_INT_EN | \
842 			       B_AX_CPU_FLOW_CTRL_ERR_INT_EN | \
843 			       B_AX_CPU_NULLPKT_ERR_INT_EN | \
844 			       B_AX_CPU_BURST_NUM_ERR_INT_EN | \
845 			       B_AX_CPU_RXAGG_CFG_ERR_INT_EN | \
846 			       B_AX_CPU_SHIFT_EN_ERR_INT_EN | \
847 			       B_AX_CPU_TOTAL_LEN_ERR_INT_EN | \
848 			       B_AX_CPU_DMA_PROCESS_ERR_INT_EN | \
849 			       B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN | \
850 			       B_AX_CPU_CHKSUM_FSM_ERR_INT_EN | \
851 			       B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN | \
852 			       B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN)
853 #define B_AX_CPU_DISP_IMR_SET (B_AX_CPU_PKT_FAIL_DBG_INT_EN | \
854 			       B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \
855 			       B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \
856 			       B_AX_CPU_TOTAL_LEN_ERR_INT_EN)
857 
858 #define B_AX_CR_PLD_LEN_ERR_INT_EN BIT(30)
859 #define B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29)
860 #define B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28)
861 #define B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27)
862 #define B_AX_CR_DMA_PROCESS_ERR_INT_EN BIT(26)
863 #define B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25)
864 #define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24)
865 #define B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22)
866 #define B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21)
867 #define B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20)
868 #define B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19)
869 #define B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17)
870 #define B_AX_CT_WD_LEN_OVER_ERR_INT_EN BIT(16)
871 #define B_AX_CT_F2P_SEQ_ERR_INT_EN BIT(15)
872 #define B_AX_CT_F2P_QSEL_ERR_INT_EN BIT(14)
873 #define B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13)
874 #define B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12)
875 #define B_AX_CT_PRE_SUB_ERR_INT_EN BIT(11)
876 #define B_AX_CT_WD_CHKSUM_ERR_INT_EN BIT(10)
877 #define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
878 #define B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8)
879 #define B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
880 #define B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
881 #define B_AX_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
882 #define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
883 #define B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
884 #define B_AX_CT_CH_ID_ERR_INT_EN BIT(2)
885 #define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
886 #define B_AX_CPU_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \
887 				  B_AX_CT_CH_ID_ERR_INT_EN | \
888 				  B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
889 				  B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
890 				  B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \
891 				  B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \
892 				  B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN | \
893 				  B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN | \
894 				  B_AX_CT_CHANNEL_DMA_ERR_INT_EN | \
895 				  B_AX_CT_WD_CHKSUM_ERR_INT_EN | \
896 				  B_AX_CT_PRE_SUB_ERR_INT_EN | \
897 				  B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
898 				  B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
899 				  B_AX_CT_F2P_QSEL_ERR_INT_EN | \
900 				  B_AX_CT_F2P_SEQ_ERR_INT_EN | \
901 				  B_AX_CT_WD_LEN_OVER_ERR_INT_EN | \
902 				  B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \
903 				  B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN | \
904 				  B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
905 				  B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN | \
906 				  B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
907 				  B_AX_CR_SHIFT_EN_ERR_INT_EN | \
908 				  B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \
909 				  B_AX_CR_DMA_PROCESS_ERR_INT_EN | \
910 				  B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN | \
911 				  B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \
912 				  B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN | \
913 				  B_AX_CR_PLD_LEN_ERR_INT_EN)
914 #define B_AX_CPU_DISP_IMR_SET_V1 (B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \
915 				  B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \
916 				  B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \
917 				  B_AX_CR_DMA_PROCESS_ERR_INT_EN | \
918 				  B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \
919 				  B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN)
920 
921 #define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858
922 #define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29)
923 #define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28)
924 #define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27)
925 #define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26)
926 #define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25)
927 #define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24)
928 #define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17)
929 #define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16)
930 #define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12)
931 #define B_AX_PLE_RESP_ERR_INT_EN BIT(11)
932 #define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10)
933 #define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9)
934 #define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8)
935 #define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4)
936 #define B_AX_WDE_RESP_ERR_INT_EN BIT(3)
937 #define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2)
938 #define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1)
939 #define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
940 #define B_AX_OTHER_DISP_IMR_CLR (B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN | \
941 				 B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN | \
942 				 B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN | \
943 				 B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN | \
944 				 B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN | \
945 				 B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN | \
946 				 B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \
947 				 B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \
948 				 B_AX_PLE_OUTPUT_ERR_INT_EN | \
949 				 B_AX_PLE_RESP_ERR_INT_EN | \
950 				 B_AX_PLE_BURST_NUM_ERR_INT_EN | \
951 				 B_AX_PLE_NULL_PKT_ERR_INT_EN | \
952 				 B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \
953 				 B_AX_WDE_OUTPUT_ERR_INT_EN | \
954 				 B_AX_WDE_RESP_ERR_INT_EN | \
955 				 B_AX_WDE_BURST_NUM_ERR_INT_EN | \
956 				 B_AX_WDE_NULL_PKT_ERR_INT_EN | \
957 				 B_AX_WDE_FLOW_CTRL_ERR_INT_EN)
958 
959 #define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31)
960 #define B_AX_REUSE_EN_ERR_INT_EN BIT(30)
961 #define B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29)
962 #define B_AX_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28)
963 #define B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27)
964 #define B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26)
965 #define B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25)
966 #define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
967 #define B_AX_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23)
968 #define B_AX_REUSE_PKT_CNT_ERR_INT_EN BIT(22)
969 #define B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21)
970 #define B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20)
971 #define B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19)
972 #define B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18)
973 #define B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17)
974 #define B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16)
975 #define B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15)
976 #define B_AX_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14)
977 #define B_AX_PLE_RESPOSE_ERR_INT_EN BIT(11)
978 #define B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
979 #define B_AX_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6)
980 #define B_AX_WDE_RESPONSE_ERR_INT_EN BIT(3)
981 #define B_AX_OTHER_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \
982 				    B_AX_WDE_FLOW_CTRL_ERR_INT_EN | \
983 				    B_AX_WDE_NULL_PKT_ERR_INT_EN | \
984 				    B_AX_WDE_BURST_NUM_ERR_INT_EN | \
985 				    B_AX_WDE_RESPONSE_ERR_INT_EN | \
986 				    B_AX_WDE_OUTPUT_ERR_INT_EN | \
987 				    B_AX_HDR_RX_TIMEOUT_ERR_INT_EN | \
988 				    B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN | \
989 				    B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \
990 				    B_AX_PLE_NULL_PKT_ERR_INT_EN | \
991 				    B_AX_PLE_BURST_NUM_ERR_INT_EN | \
992 				    B_AX_PLE_RESPOSE_ERR_INT_EN | \
993 				    B_AX_PLE_OUTPUT_ERR_INT_EN | \
994 				    B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \
995 				    B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \
996 				    B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN | \
997 				    B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN | \
998 				    B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \
999 				    B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \
1000 				    B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \
1001 				    B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \
1002 				    B_AX_REUSE_PKT_CNT_ERR_INT_EN | \
1003 				    B_AX_REUSE_SIZE_ZERO_ERR_INT_EN | \
1004 				    B_AX_STF_CMD_OVERFLOW_ERR_INT_EN | \
1005 				    B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN | \
1006 				    B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN | \
1007 				    B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
1008 				    B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
1009 				    B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN | \
1010 				    B_AX_REUSE_EN_ERR_INT_EN | \
1011 				    B_AX_REUSE_SIZE_ERR_INT_EN)
1012 #define B_AX_OTHER_DISP_IMR_SET_V1 (B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \
1013 				    B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \
1014 				    B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \
1015 				    B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \
1016 				    B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \
1017 				    B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \
1018 				    B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
1019 				    B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN)
1020 
1021 #define R_AX_DISPATCHER_DBG_PORT 0x8860
1022 #define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8)
1023 #define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
1024 #define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)
1025 
1026 #define R_AX_RX_FUNCTION_STOP 0x8920
1027 #define B_AX_HDR_RX_STOP BIT(0)
1028 
1029 #define R_AX_HCI_FC_CTRL 0x8A00
1030 #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
1031 #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
1032 #define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
1033 #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
1034 #define B_AX_HCI_FC_CH12_EN BIT(3)
1035 #define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1)
1036 #define B_AX_HCI_FC_EN BIT(0)
1037 
1038 #define R_AX_CH_PAGE_CTRL 0x8A04
1039 #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
1040 #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
1041 
1042 #define B_AX_MAX_PG_MASK GENMASK(28, 16)
1043 #define B_AX_MIN_PG_MASK GENMASK(12, 0)
1044 #define B_AX_GRP BIT(31)
1045 #define R_AX_ACH0_PAGE_CTRL 0x8A10
1046 #define R_AX_ACH1_PAGE_CTRL 0x8A14
1047 #define R_AX_ACH2_PAGE_CTRL 0x8A18
1048 #define R_AX_ACH3_PAGE_CTRL 0x8A1C
1049 #define R_AX_ACH4_PAGE_CTRL 0x8A20
1050 #define R_AX_ACH5_PAGE_CTRL 0x8A24
1051 #define R_AX_ACH6_PAGE_CTRL 0x8A28
1052 #define R_AX_ACH7_PAGE_CTRL 0x8A2C
1053 #define R_AX_CH8_PAGE_CTRL 0x8A30
1054 #define R_AX_CH9_PAGE_CTRL 0x8A34
1055 #define R_AX_CH10_PAGE_CTRL 0x8A38
1056 #define R_AX_CH11_PAGE_CTRL 0x8A3C
1057 
1058 #define B_AX_AVAL_PG_MASK GENMASK(27, 16)
1059 #define B_AX_USE_PG_MASK GENMASK(12, 0)
1060 #define R_AX_ACH0_PAGE_INFO 0x8A50
1061 #define R_AX_ACH1_PAGE_INFO 0x8A54
1062 #define R_AX_ACH2_PAGE_INFO 0x8A58
1063 #define R_AX_ACH3_PAGE_INFO 0x8A5C
1064 #define R_AX_ACH4_PAGE_INFO 0x8A60
1065 #define R_AX_ACH5_PAGE_INFO 0x8A64
1066 #define R_AX_ACH6_PAGE_INFO 0x8A68
1067 #define R_AX_ACH7_PAGE_INFO 0x8A6C
1068 #define R_AX_CH8_PAGE_INFO 0x8A70
1069 #define R_AX_CH9_PAGE_INFO 0x8A74
1070 #define R_AX_CH10_PAGE_INFO 0x8A78
1071 #define R_AX_CH11_PAGE_INFO 0x8A7C
1072 #define R_AX_CH12_PAGE_INFO 0x8A80
1073 
1074 #define R_AX_PUB_PAGE_INFO3 0x8A8C
1075 #define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16)
1076 #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
1077 
1078 #define R_AX_PUB_PAGE_CTRL1 0x8A90
1079 #define B_AX_PUBPG_G1_MASK GENMASK(28, 16)
1080 #define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
1081 
1082 #define R_AX_PUB_PAGE_CTRL2 0x8A94
1083 #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
1084 
1085 #define R_AX_PUB_PAGE_INFO1 0x8A98
1086 #define B_AX_G1_USE_PG_MASK GENMASK(28, 16)
1087 #define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
1088 
1089 #define R_AX_PUB_PAGE_INFO2 0x8A9C
1090 #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
1091 
1092 #define R_AX_WP_PAGE_CTRL1 0x8AA0
1093 #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
1094 #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
1095 
1096 #define R_AX_WP_PAGE_CTRL2 0x8AA4
1097 #define B_AX_WP_THRD_MASK GENMASK(12, 0)
1098 
1099 #define R_AX_WP_PAGE_INFO1 0x8AA8
1100 #define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16)
1101 
1102 #define R_AX_WDE_PKTBUF_CFG 0x8C08
1103 #define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8)
1104 #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
1105 #define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1106 
1107 #define R_AX_WDE_ERRFLAG_MSG 0x8C30
1108 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1109 
1110 #define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34
1111 #define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31)
1112 #define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1113 #define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
1114 #define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2)
1115 #define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1)
1116 #define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0)
1117 
1118 #define R_AX_WDE_ERR_IMR 0x8C38
1119 #define B_AX_WDE_DATCHN_UAPG_ERR_INT_EN BIT(30)
1120 #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
1121 #define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
1122 #define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
1123 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1124 #define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
1125 #define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
1126 #define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
1127 #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
1128 #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
1129 #define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
1130 #define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
1131 #define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
1132 #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
1133 #define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
1134 #define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5)
1135 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1136 #define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
1137 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
1138 #define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
1139 #define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1140 #define B_AX_WDE_IMR_CLR (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1141 			  B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1142 			  B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1143 			  B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1144 			  B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1145 			  B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1146 			  B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1147 			  B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1148 			  B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1149 			  B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1150 			  B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1151 			  B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1152 			  B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1153 			  B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1154 			  B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1155 			  B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1156 			  B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1157 			  B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1158 			  B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN)
1159 #define B_AX_WDE_IMR_CLR_V01 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1160 			      B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1161 			      B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1162 			      B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1163 			      B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1164 			      B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1165 			      B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1166 			      B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1167 			      B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1168 			      B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1169 			      B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1170 			      B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1171 			      B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1172 			      B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1173 			      B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1174 			      B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1175 			      B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1176 			      B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1177 			      B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1178 			      B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1179 			      B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1180 			      B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN | \
1181 			      B_AX_WDE_DATCHN_UAPG_ERR_INT_EN)
1182 #define B_AX_WDE_IMR_SET (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1183 			  B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1184 			  B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1185 			  B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1186 			  B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1187 			  B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1188 			  B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1189 			  B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1190 			  B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1191 			  B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1192 			  B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1193 			  B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1194 			  B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1195 			  B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1196 			  B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1197 			  B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1198 			  B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1199 			  B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1200 			  B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN)
1201 #define B_AX_WDE_IMR_SET_V01 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1202 			      B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
1203 			      B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1204 			      B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
1205 			      B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1206 			      B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
1207 			      B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
1208 			      B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
1209 			      B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1210 			      B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1211 			      B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1212 			      B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1213 			      B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1214 			      B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1215 			      B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1216 			      B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1217 			      B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1218 			      B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1219 			      B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1220 			      B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1221 			      B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1222 			      B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
1223 
1224 #define B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
1225 #define B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
1226 #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
1227 #define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
1228 #define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
1229 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1230 #define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
1231 #define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
1232 #define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
1233 #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
1234 #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
1235 #define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
1236 #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1237 #define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
1238 #define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1239 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
1240 #define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
1241 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1242 #define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1243 #define B_AX_WDE_BUFREQ_SIZELMT_INT_EN BIT(2)
1244 #define B_AX_WDE_BUFREQ_SIZE0_INT_EN BIT(1)
1245 #define B_AX_WDE_IMR_CLR_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1246 			     B_AX_WDE_BUFREQ_SIZE0_INT_EN | \
1247 			     B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \
1248 			     B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1249 			     B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1250 			     B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1251 			     B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1252 			     B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1253 			     B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1254 			     B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1255 			     B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1256 			     B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1257 			     B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1258 			     B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1259 			     B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1260 			     B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1261 			     B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1262 			     B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1263 			     B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1264 			     B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1265 			     B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1266 			     B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1267 			     B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1268 			     B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
1269 #define B_AX_WDE_IMR_SET_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
1270 			     B_AX_WDE_BUFREQ_SIZE0_INT_EN | \
1271 			     B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \
1272 			     B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1273 			     B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1274 			     B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1275 			     B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1276 			     B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1277 			     B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1278 			     B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1279 			     B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
1280 			     B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
1281 			     B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
1282 			     B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1283 			     B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1284 			     B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
1285 			     B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
1286 			     B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
1287 			     B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
1288 			     B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
1289 			     B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
1290 			     B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
1291 			     B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
1292 			     B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
1293 
1294 #define R_AX_WDE_ERR_ISR 0x8C3C
1295 #define B_AX_WDE_DATCHN_RRDY_ERR BIT(27)
1296 #define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26)
1297 #define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25)
1298 #define B_AX_WDE_DATCHN_ARBT_ERR BIT(24)
1299 #define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19)
1300 #define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18)
1301 #define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17)
1302 #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16)
1303 #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15)
1304 #define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14)
1305 #define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13)
1306 #define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12)
1307 #define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7)
1308 #define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6)
1309 #define B_AX_WDE_GETNPG_STRPG_ERR BIT(5)
1310 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4)
1311 #define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3)
1312 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2)
1313 #define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1)
1314 #define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0)
1315 
1316 #define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16)
1317 #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
1318 #define R_AX_WDE_QTA0_CFG 0x8C40
1319 #define R_AX_WDE_QTA1_CFG 0x8C44
1320 #define R_AX_WDE_QTA2_CFG 0x8C48
1321 #define R_AX_WDE_QTA3_CFG 0x8C4C
1322 #define R_AX_WDE_QTA4_CFG 0x8C50
1323 
1324 #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
1325 #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
1326 #define B_AX_DLE_FREE_TAILPG GENMASK(27, 16)
1327 #define B_AX_DLE_USE_PGNUM GENMASK(27, 16)
1328 #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
1329 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1330 
1331 #define R_AX_WDE_INI_STATUS 0x8D00
1332 #define B_AX_WDE_Q_MGN_INI_RDY BIT(1)
1333 #define B_AX_WDE_BUF_MGN_INI_RDY BIT(0)
1334 #define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY)
1335 #define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10
1336 #define B_AX_WDE_DFI_ACTIVE BIT(31)
1337 #define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16)
1338 #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
1339 #define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14
1340 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1341 
1342 #define R_AX_PLE_PKTBUF_CFG 0x9008
1343 #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
1344 #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
1345 #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1346 
1347 #define R_AX_PLE_DBGERR_LOCKEN 0x9020
1348 #define B_AX_PLE_LOCKEN_DLEPIF07 BIT(7)
1349 #define B_AX_PLE_LOCKEN_DLEPIF06 BIT(6)
1350 #define B_AX_PLE_LOCKEN_DLEPIF05 BIT(5)
1351 #define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4)
1352 #define B_AX_PLE_LOCKEN_DLEPIF03 BIT(3)
1353 #define B_AX_PLE_LOCKEN_DLEPIF02 BIT(2)
1354 #define B_AX_PLE_LOCKEN_DLEPIF01 BIT(1)
1355 #define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0)
1356 
1357 #define R_AX_PLE_DBGERR_STS 0x9024
1358 #define B_AX_PLE_LOCKON_DLEPIF07 BIT(7)
1359 #define B_AX_PLE_LOCKON_DLEPIF06 BIT(6)
1360 #define B_AX_PLE_LOCKON_DLEPIF05 BIT(5)
1361 #define B_AX_PLE_LOCKON_DLEPIF04 BIT(4)
1362 #define B_AX_PLE_LOCKON_DLEPIF03 BIT(3)
1363 #define B_AX_PLE_LOCKON_DLEPIF02 BIT(2)
1364 #define B_AX_PLE_LOCKON_DLEPIF01 BIT(1)
1365 #define B_AX_PLE_LOCKON_DLEPIF00 BIT(0)
1366 
1367 #define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034
1368 #define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31)
1369 #define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1370 #define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
1371 #define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2)
1372 #define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1)
1373 #define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0)
1374 
1375 #define R_AX_PLE_ERRFLAG_MSG 0x9030
1376 #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1377 #define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
1378 #define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
1379 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1380 #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
1381 #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1382 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
1383 #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
1384 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1385 #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1386 #define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
1387 #define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
1388 #define B_AX_PLE_DATCHN_CAMREQ_ERR BIT(29)
1389 #define B_AX_PLE_DATCHN_ADRERR_ERR BIT(28)
1390 #define B_AX_PLE_BUFMGN_FRZTO_ERR_V1 BIT(9)
1391 #define B_AX_PLE_GETNPG_PGOFST_ERR_V1 BIT(8)
1392 #define B_AX_PLE_GETNPG_STRPG_ERR_V1 BIT(7)
1393 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_V1 BIT(6)
1394 #define B_AX_PLE_BUFRTN_SIZE_ERR_V1 BIT(5)
1395 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4)
1396 #define B_AX_PLE_BUFREQ_UNAVAL_ERR_V1 BIT(3)
1397 #define B_AX_PLE_BUFREQ_SIZELMT_ERR BIT(2)
1398 #define B_AX_PLE_BUFREQ_SIZE0_ERR BIT(1)
1399 
1400 #define R_AX_PLE_ERR_IMR 0x9038
1401 #define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
1402 #define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
1403 #define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
1404 #define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1405 #define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
1406 #define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
1407 #define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
1408 #define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
1409 #define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
1410 #define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
1411 #define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
1412 #define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
1413 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
1414 #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
1415 #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5)
1416 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
1417 #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
1418 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
1419 #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
1420 #define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1421 #define B_AX_PLE_IMR_CLR (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1422 			  B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
1423 			  B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1424 			  B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \
1425 			  B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1426 			  B_AX_PLE_GETNPG_STRPG_ERR_INT_EN | \
1427 			  B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \
1428 			  B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
1429 			  B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1430 			  B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1431 			  B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1432 			  B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1433 			  B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1434 			  B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1435 			  B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1436 			  B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1437 			  B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1438 			  B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1439 			  B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN)
1440 #define B_AX_PLE_IMR_SET (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1441 			  B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
1442 			  B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
1443 			  B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \
1444 			  B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
1445 			  B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \
1446 			  B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
1447 			  B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1448 			  B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1449 			  B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1450 			  B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1451 			  B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1452 			  B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1453 			  B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1454 			  B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1455 			  B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1456 			  B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1457 			  B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN)
1458 
1459 #define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
1460 #define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
1461 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1462 #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
1463 #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
1464 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
1465 #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
1466 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
1467 #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
1468 #define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
1469 #define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
1470 #define B_AX_PLE_IMR_CLR_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1471 			     B_AX_PLE_BUFREQ_SIZE0_INT_EN | \
1472 			     B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \
1473 			     B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1474 			     B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1475 			     B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1476 			     B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1477 			     B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1478 			     B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1479 			     B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1480 			     B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1481 			     B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1482 			     B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1483 			     B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1484 			     B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1485 			     B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1486 			     B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1487 			     B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1488 			     B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1489 			     B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1490 			     B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \
1491 			     B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \
1492 			     B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \
1493 			     B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN)
1494 #define B_AX_PLE_IMR_SET_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
1495 			     B_AX_PLE_BUFREQ_SIZE0_INT_EN | \
1496 			     B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \
1497 			     B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
1498 			     B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
1499 			     B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
1500 			     B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
1501 			     B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \
1502 			     B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
1503 			     B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
1504 			     B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
1505 			     B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
1506 			     B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
1507 			     B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
1508 			     B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
1509 			     B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
1510 			     B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
1511 			     B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
1512 			     B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
1513 			     B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
1514 			     B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \
1515 			     B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \
1516 			     B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \
1517 			     B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN)
1518 
1519 #define R_AX_PLE_ERR_FLAG_ISR 0x903C
1520 #define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16)
1521 #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
1522 #define R_AX_PLE_QTA0_CFG 0x9040
1523 #define R_AX_PLE_QTA1_CFG 0x9044
1524 #define R_AX_PLE_QTA2_CFG 0x9048
1525 #define R_AX_PLE_QTA3_CFG 0x904C
1526 #define R_AX_PLE_QTA4_CFG 0x9050
1527 #define R_AX_PLE_QTA5_CFG 0x9054
1528 #define R_AX_PLE_QTA6_CFG 0x9058
1529 #define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
1530 #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
1531 #define R_AX_PLE_QTA7_CFG 0x905C
1532 #define B_AX_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16)
1533 #define B_AX_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)
1534 #define R_AX_PLE_QTA8_CFG 0x9060
1535 #define R_AX_PLE_QTA9_CFG 0x9064
1536 #define R_AX_PLE_QTA10_CFG 0x9068
1537 #define R_AX_PLE_QTA11_CFG 0x906C
1538 
1539 #define R_AX_PLE_INI_STATUS 0x9100
1540 #define B_AX_PLE_Q_MGN_INI_RDY BIT(1)
1541 #define B_AX_PLE_BUF_MGN_INI_RDY BIT(0)
1542 #define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY)
1543 #define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110
1544 #define B_AX_PLE_DFI_ACTIVE BIT(31)
1545 #define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
1546 #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
1547 #define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114
1548 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1549 
1550 #define R_AX_WDRLS_CFG 0x9408
1551 #define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
1552 #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
1553 
1554 #define R_AX_RLSRPT0_CFG0 0x9410
1555 #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
1556 #define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16)
1557 #define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8)
1558 #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
1559 
1560 #define R_AX_RLSRPT0_CFG1 0x9414
1561 #define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16)
1562 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1563 
1564 #define R_AX_WDRLS_ERR_IMR 0x9430
1565 #define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13)
1566 #define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12)
1567 #define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
1568 #define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8)
1569 #define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5)
1570 #define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
1571 #define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2)
1572 #define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1)
1573 #define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
1574 #define B_AX_WDRLS_IMR_EN_CLR (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
1575 			       B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
1576 			       B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
1577 			       B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
1578 			       B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
1579 			       B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
1580 			       B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
1581 			       B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
1582 			       B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
1583 #define B_AX_WDRLS_IMR_SET (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
1584 			    B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
1585 			    B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
1586 			    B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
1587 			    B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
1588 			    B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
1589 			    B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
1590 			    B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
1591 #define B_AX_WDRLS_IMR_SET_V1 (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
1592 			      B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
1593 			      B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
1594 			      B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
1595 			      B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
1596 			      B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
1597 			      B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
1598 			      B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
1599 			      B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
1600 
1601 #define R_AX_WDRLS_ERR_ISR 0x9434
1602 
1603 #define R_AX_BBRPT_COM_ERR_IMR 0x9608
1604 #define B_AX_BBRPT_COM_HANG_EN BIT(1)
1605 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1606 
1607 #define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C
1608 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16)
1609 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1610 
1611 #define R_AX_BBRPT_COM_ERR_ISR 0x960C
1612 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0)
1613 
1614 #define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C
1615 #define B_AX_BBPRT_CHIF_TO_ERR_V1 BIT(7)
1616 #define B_AX_BBPRT_CHIF_NULL_ERR_V1 BIT(6)
1617 #define B_AX_BBPRT_CHIF_LEFT2_ERR_V1 BIT(5)
1618 #define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4)
1619 #define B_AX_BBPRT_CHIF_HDRL_ERR_V1 BIT(3)
1620 #define B_AX_BBPRT_CHIF_BOVF_ERR_V1 BIT(2)
1621 #define B_AX_BBPRT_CHIF_OVF_ERR_V1 BIT(1)
1622 #define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0)
1623 
1624 #define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628
1625 #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
1626 #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
1627 #define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5)
1628 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1629 #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
1630 #define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2)
1631 #define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1)
1632 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1633 #define R_AX_BBRPT_CHINFO_IMR_SET_V1 (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \
1634 				      B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \
1635 				      B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \
1636 				      B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \
1637 				      B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \
1638 				      B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \
1639 				      B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \
1640 				      B_AX_BBPRT_CHIF_TO_ERR_INT_EN)
1641 
1642 #define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C
1643 #define B_AX_BBPRT_CHIF_TO_ERR BIT(23)
1644 #define B_AX_BBPRT_CHIF_NULL_ERR BIT(22)
1645 #define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21)
1646 #define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20)
1647 #define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19)
1648 #define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18)
1649 #define B_AX_BBPRT_CHIF_OVF_ERR BIT(17)
1650 #define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16)
1651 #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
1652 #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
1653 #define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5)
1654 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
1655 #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
1656 #define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2)
1657 #define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1)
1658 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1659 #define B_AX_BBRPT_CHINFO_IMR_CLR (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \
1660 				   B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \
1661 				   B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \
1662 				   B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \
1663 				   B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \
1664 				   B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \
1665 				   B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \
1666 				   B_AX_BBPRT_CHIF_TO_ERR_INT_EN)
1667 
1668 #define R_AX_BBRPT_DFS_ERR_IMR 0x9638
1669 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1670 
1671 #define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C
1672 #define B_AX_BBRPT_DFS_TO_ERR BIT(16)
1673 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1674 
1675 #define R_AX_BBRPT_DFS_ERR_ISR 0x963C
1676 #define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0)
1677 
1678 #define R_AX_LA_ERRFLAG 0x966C
1679 #define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16)
1680 #define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
1681 
1682 #define R_AX_WD_BUF_REQ 0x9800
1683 #define R_AX_PL_BUF_REQ 0x9820
1684 #define B_AX_WD_BUF_REQ_EXEC BIT(31)
1685 #define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
1686 #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
1687 
1688 #define R_AX_WD_BUF_STATUS 0x9804
1689 #define R_AX_PL_BUF_STATUS 0x9824
1690 #define B_AX_WD_BUF_STAT_DONE BIT(31)
1691 #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
1692 #define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0)
1693 
1694 #define R_AX_WD_CPUQ_OP_0 0x9810
1695 #define R_AX_PL_CPUQ_OP_0 0x9830
1696 #define B_AX_WD_CPUQ_OP_EXEC BIT(31)
1697 #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
1698 #define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16)
1699 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1700 
1701 #define R_AX_WD_CPUQ_OP_1 0x9814
1702 #define R_AX_PL_CPUQ_OP_1 0x9834
1703 #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
1704 #define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16)
1705 #define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6)
1706 #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
1707 
1708 #define R_AX_WD_CPUQ_OP_2 0x9818
1709 #define R_AX_PL_CPUQ_OP_2 0x9838
1710 #define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
1711 #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
1712 
1713 #define R_AX_WD_CPUQ_OP_STATUS 0x981C
1714 #define R_AX_PL_CPUQ_OP_STATUS 0x983C
1715 #define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
1716 #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
1717 
1718 #define R_AX_CPUIO_ERR_IMR 0x9840
1719 #define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12)
1720 #define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8)
1721 #define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4)
1722 #define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0)
1723 #define B_AX_CPUIO_IMR_CLR (B_AX_WDEBUF_OP_ERR_INT_EN | \
1724 			    B_AX_WDEQUE_OP_ERR_INT_EN | \
1725 			    B_AX_PLEBUF_OP_ERR_INT_EN | \
1726 			    B_AX_PLEQUE_OP_ERR_INT_EN)
1727 #define B_AX_CPUIO_IMR_SET (B_AX_WDEBUF_OP_ERR_INT_EN | \
1728 			    B_AX_WDEQUE_OP_ERR_INT_EN | \
1729 			    B_AX_PLEBUF_OP_ERR_INT_EN | \
1730 			    B_AX_PLEQUE_OP_ERR_INT_EN)
1731 
1732 #define R_AX_CPUIO_ERR_ISR 0x9844
1733 
1734 #define R_AX_SEC_ERR_IMR_ISR 0x991C
1735 
1736 #define R_AX_PKTIN_SETTING 0x9A00
1737 #define B_AX_WD_ADDR_INFO_LENGTH BIT(1)
1738 
1739 #define R_AX_PKTIN_ERR_IMR 0x9A20
1740 #define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0)
1741 
1742 #define R_AX_PKTIN_ERR_ISR 0x9A24
1743 
1744 #define R_AX_MPDU_TX_ERR_ISR 0x9BF0
1745 #define R_AX_MPDU_TX_ERR_IMR 0x9BF4
1746 #define B_AX_TX_KSRCH_ERR_EN BIT(9)
1747 #define B_AX_TX_NW_TYPE_ERR_EN BIT(8)
1748 #define B_AX_TX_LLC_PRE_ERR_EN BIT(7)
1749 #define B_AX_TX_ETH_TYPE_ERR_EN BIT(6)
1750 #define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5)
1751 #define B_AX_TX_OFFSET_ERR_INT_EN BIT(4)
1752 #define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3)
1753 #define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2)
1754 #define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1)
1755 #define B_AX_MPDU_TX_IMR_SET_V1 (B_AX_TX_GET_ERRPKTID_INT_EN | \
1756 				 B_AX_TX_NXT_ERRPKTID_INT_EN | \
1757 				 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | \
1758 				 B_AX_TX_HDR3_SIZE_ERR_INT_EN | \
1759 				 B_AX_TX_ETH_TYPE_ERR_EN | \
1760 				 B_AX_TX_NW_TYPE_ERR_EN | \
1761 				 B_AX_TX_KSRCH_ERR_EN)
1762 
1763 #define R_AX_MPDU_PROC 0x9C00
1764 #define B_AX_A_ICV_ERR BIT(1)
1765 #define B_AX_APPEND_FCS BIT(0)
1766 
1767 #define R_AX_ACTION_FWD0 0x9C04
1768 #define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
1769 
1770 #define R_AX_ACTION_FWD1 0x9C08
1771 
1772 #define R_AX_TF_FWD 0x9C14
1773 #define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
1774 
1775 #define R_AX_HW_RPT_FWD 0x9C18
1776 #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
1777 #define RTW89_PRPT_DEST_HOST 1
1778 #define RTW89_PRPT_DEST_WLCPU 2
1779 
1780 #define R_AX_CUT_AMSDU_CTRL 0x9C40
1781 #define TRXCFG_MPDU_PROC_CUT_CTRL	0x010E05F0
1782 
1783 #define R_AX_WOW_CTRL 0x9C50
1784 #define B_AX_WOW_WOWEN BIT(1)
1785 
1786 #define R_AX_MPDU_RX_ERR_ISR 0x9CF0
1787 #define R_AX_MPDU_RX_ERR_IMR 0x9CF4
1788 #define B_AX_RPT_ERR_INT_EN BIT(3)
1789 #define B_AX_MHDRLEN_ERR_INT_EN BIT(1)
1790 #define B_AX_GETPKTID_ERR_INT_EN BIT(0)
1791 #define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN
1792 
1793 #define R_AX_SEC_ENG_CTRL 0x9D00
1794 #define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16)
1795 #define B_AX_TX_PARTIAL_MODE BIT(11)
1796 #define B_AX_CLK_EN_CGCMP BIT(10)
1797 #define B_AX_CLK_EN_WAPI BIT(9)
1798 #define B_AX_CLK_EN_WEP_TKIP BIT(8)
1799 #define B_AX_BMC_MGNT_DEC BIT(5)
1800 #define B_AX_UC_MGNT_DEC BIT(4)
1801 #define B_AX_MC_DEC BIT(3)
1802 #define B_AX_BC_DEC BIT(2)
1803 #define B_AX_SEC_RX_DEC BIT(1)
1804 #define B_AX_SEC_TX_ENC BIT(0)
1805 
1806 #define R_AX_SEC_MPDU_PROC 0x9D04
1807 #define B_AX_APPEND_ICV BIT(1)
1808 #define B_AX_APPEND_MIC BIT(0)
1809 
1810 #define R_AX_SEC_CAM_ACCESS 0x9D10
1811 #define R_AX_SEC_CAM_RDATA 0x9D14
1812 #define R_AX_SEC_CAM_WDATA 0x9D18
1813 
1814 #define R_AX_SEC_DEBUG 0x9D1C
1815 #define B_AX_IMR_ERROR BIT(3)
1816 
1817 #define R_AX_SEC_DEBUG1 0x9D1C
1818 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1819 #define AX_TX_TO_VAL  0x2
1820 
1821 #define R_AX_SEC_TX_DEBUG 0x9D20
1822 #define R_AX_SEC_RX_DEBUG 0x9D24
1823 #define R_AX_SEC_TRX_PKT_CNT 0x9D28
1824 
1825 #define R_AX_SEC_DEBUG2 0x9D28
1826 #define B_AX_DBG_READ_SH 2
1827 #define B_AX_DBG_READ_MSK 0x3fffffff
1828 
1829 #define R_AX_SEC_TRX_BLK_CNT 0x9D2C
1830 
1831 #define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C
1832 #define B_AX_RX_HANG_IMR BIT(1)
1833 #define B_AX_TX_HANG_IMR BIT(0)
1834 
1835 #define R_AX_SEC_ERROR_FLAG 0x9D30
1836 #define B_AX_RX_HANG_ERROR_V1 BIT(1)
1837 #define B_AX_TX_HANG_ERROR_V1 BIT(0)
1838 
1839 #define R_AX_SS_CTRL 0x9E10
1840 #define B_AX_SS_INIT_DONE_1 BIT(31)
1841 #define B_AX_SS_WARM_INIT_FLG BIT(29)
1842 #define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28)
1843 #define B_AX_SS_EN BIT(0)
1844 
1845 #define R_AX_SS2FINFO_PATH 0x9E50
1846 #define B_AX_SS_UL_REL BIT(31)
1847 #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
1848 #define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)
1849 #define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)
1850 #define SS2F_PATH_WLCPU 0x0A
1851 #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
1852 
1853 #define R_AX_SS_MACID_PAUSE_0 0x9EB0
1854 #define B_AX_SS_MACID31_0_PAUSE_SH 0
1855 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1856 
1857 #define R_AX_SS_MACID_PAUSE_1 0x9EB4
1858 #define B_AX_SS_MACID63_32_PAUSE_SH 0
1859 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1860 
1861 #define R_AX_SS_MACID_PAUSE_2 0x9EB8
1862 #define B_AX_SS_MACID95_64_PAUSE_SH 0
1863 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1864 
1865 #define R_AX_SS_MACID_PAUSE_3 0x9EBC
1866 #define B_AX_SS_MACID127_96_PAUSE_SH 0
1867 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1868 
1869 #define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0
1870 #define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2)
1871 #define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1)
1872 #define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0)
1873 #define B_AX_STA_SCHEDULER_IMR_SET (B_AX_SEARCH_HANG_TIMEOUT_INT_EN | \
1874 				    B_AX_RPT_HANG_TIMEOUT_INT_EN | \
1875 				    B_AX_PLE_B_PKTID_ERR_INT_EN)
1876 
1877 #define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4
1878 
1879 #define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C
1880 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25)
1881 #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24)
1882 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19)
1883 #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18)
1884 #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17)
1885 #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16)
1886 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1887 #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8)
1888 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
1889 #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
1890 #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
1891 #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0)
1892 #define B_AX_TXPKTCTL_IMR_B0_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1893 				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
1894 				  B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \
1895 				  B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \
1896 				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
1897 				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
1898 #define B_AX_TXPKTCTL_IMR_B1_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1899 				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
1900 				  B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \
1901 				  B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \
1902 				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
1903 				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
1904 #define B_AX_TXPKTCTL_IMR_B0_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1905 				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN)
1906 #define B_AX_TXPKTCTL_IMR_B1_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
1907 				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
1908 				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
1909 				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
1910 
1911 #define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C
1912 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1913 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
1914 #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
1915 #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
1916 
1917 #define R_AX_DBG_FUN_INTF_CTL 0x9F30
1918 #define B_AX_DFI_ACTIVE BIT(31)
1919 #define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16)
1920 #define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
1921 #define R_AX_DBG_FUN_INTF_DATA 0x9F34
1922 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1923 
1924 #define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48
1925 #define B_AX_B0_PRELD_FEN BIT(31)
1926 #define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1927 #define PRELD_B0_ENT_NUM 10
1928 #define PRELD_AMSDU_SIZE 52
1929 #define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1930 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1931 
1932 #define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
1933 #define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1934 #define PRELD_NEXT_WND 1
1935 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1936 
1937 #define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
1938 #define B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(21)
1939 #define B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(20)
1940 #define B_AX_B0_IMR_ERR_MPDUIF_DATAERR BIT(18)
1941 #define B_AX_B0_IMR_ERR_MPDUINFO_RECFG BIT(16)
1942 #define B_AX_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11)
1943 #define B_AX_B0_IMR_ERR_CMDPSR_FRZTO BIT(10)
1944 #define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
1945 #define B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
1946 #define B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
1947 #define B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD BIT(2)
1948 #define B_AX_B0_IMR_ERR_USRCTL_NOINIT BIT(1)
1949 #define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0)
1950 #define B_AX_TXPKTCTL_IMR_B0_CLR_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \
1951 				     B_AX_B0_IMR_ERR_USRCTL_NOINIT | \
1952 				     B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD | \
1953 				     B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN | \
1954 				     B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \
1955 				     B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \
1956 				     B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \
1957 				     B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \
1958 				     B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \
1959 				     B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \
1960 				     B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
1961 				     B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
1962 #define B_AX_TXPKTCTL_IMR_B0_SET_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \
1963 				     B_AX_B0_IMR_ERR_USRCTL_NOINIT | \
1964 				     B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \
1965 				     B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \
1966 				     B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \
1967 				     B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \
1968 				     B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \
1969 				     B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
1970 				     B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
1971 
1972 #define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C
1973 #define B_AX_B0_ISR_ERR_PRELD_EVT3 BIT(23)
1974 #define B_AX_B0_ISR_ERR_PRELD_EVT2 BIT(22)
1975 #define B_AX_B0_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
1976 #define B_AX_B0_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
1977 #define B_AX_B0_ISR_ERR_MPDUIF_ERR1 BIT(19)
1978 #define B_AX_B0_ISR_ERR_MPDUIF_DATAERR BIT(18)
1979 #define B_AX_B0_ISR_ERR_MPDUINFO_ERR1 BIT(17)
1980 #define B_AX_B0_ISR_ERR_MPDUINFO_RECFG BIT(16)
1981 #define B_AX_B0_ISR_ERR_CMDPSR_TBLSZ BIT(11)
1982 #define B_AX_B0_ISR_ERR_CMDPSR_FRZTO BIT(10)
1983 #define B_AX_B0_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
1984 #define B_AX_B0_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
1985 #define B_AX_B0_ISR_ERR_USRCTL_EVT7 BIT(7)
1986 #define B_AX_B0_ISR_ERR_USRCTL_EVT6 BIT(6)
1987 #define B_AX_B0_ISR_ERR_USRCTL_EVT5 BIT(5)
1988 #define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4)
1989 #define B_AX_B0_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
1990 #define B_AX_B0_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
1991 #define B_AX_B0_ISR_ERR_USRCTL_NOINIT BIT(1)
1992 #define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0)
1993 
1994 #define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88
1995 #define B_AX_B1_PRELD_FEN BIT(31)
1996 #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1997 #define PRELD_B1_ENT_NUM 4
1998 #define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1999 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
2000 
2001 #define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
2002 #define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
2003 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
2004 
2005 #define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
2006 #define B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(21)
2007 #define B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(20)
2008 #define B_AX_B1_IMR_ERR_MPDUIF_DATAERR BIT(18)
2009 #define B_AX_B1_IMR_ERR_MPDUINFO_RECFG BIT(16)
2010 #define B_AX_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11)
2011 #define B_AX_B1_IMR_ERR_CMDPSR_FRZTO BIT(10)
2012 #define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
2013 #define B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
2014 #define B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
2015 #define B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD BIT(2)
2016 #define B_AX_B1_IMR_ERR_USRCTL_NOINIT BIT(1)
2017 #define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0)
2018 #define B_AX_TXPKTCTL_IMR_B1_CLR_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \
2019 				     B_AX_B1_IMR_ERR_USRCTL_NOINIT | \
2020 				     B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD | \
2021 				     B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN | \
2022 				     B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \
2023 				     B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \
2024 				     B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \
2025 				     B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \
2026 				     B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \
2027 				     B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \
2028 				     B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
2029 				     B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
2030 #define B_AX_TXPKTCTL_IMR_B1_SET_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \
2031 				     B_AX_B1_IMR_ERR_USRCTL_NOINIT | \
2032 				     B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \
2033 				     B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \
2034 				     B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \
2035 				     B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \
2036 				     B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \
2037 				     B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \
2038 				     B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
2039 				     B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
2040 
2041 #define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC
2042 #define B_AX_B1_ISR_ERR_PRELD_EVT3 BIT(23)
2043 #define B_AX_B1_ISR_ERR_PRELD_EVT2 BIT(22)
2044 #define B_AX_B1_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
2045 #define B_AX_B1_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
2046 #define B_AX_B1_ISR_ERR_MPDUIF_ERR1 BIT(19)
2047 #define B_AX_B1_ISR_ERR_MPDUIF_DATAERR BIT(18)
2048 #define B_AX_B1_ISR_ERR_MPDUINFO_ERR1 BIT(17)
2049 #define B_AX_B1_ISR_ERR_MPDUINFO_RECFG BIT(16)
2050 #define B_AX_B1_ISR_ERR_CMDPSR_TBLSZ BIT(11)
2051 #define B_AX_B1_ISR_ERR_CMDPSR_FRZTO BIT(10)
2052 #define B_AX_B1_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
2053 #define B_AX_B1_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
2054 #define B_AX_B1_ISR_ERR_USRCTL_EVT7 BIT(7)
2055 #define B_AX_B1_ISR_ERR_USRCTL_EVT6 BIT(6)
2056 #define B_AX_B1_ISR_ERR_USRCTL_EVT5 BIT(5)
2057 #define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4)
2058 #define B_AX_B1_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
2059 #define B_AX_B1_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
2060 #define B_AX_B1_ISR_ERR_USRCTL_NOINIT BIT(1)
2061 #define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0)
2062 
2063 #define R_AX_AFE_CTRL1 0x0024
2064 
2065 #define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
2066 #define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
2067 #define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
2068 #define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
2069 #define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0)
2070 
2071 #define R_AX_SYS_ISO_CTRL_EXTEND 0x0080
2072 #define B_AX_CMAC1_FEN BIT(30)
2073 #define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17)
2074 #define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16)
2075 #define B_AX_R_SYM_ISO_CMAC12PP BIT(5)
2076 
2077 #define R_AX_CMAC_REG_START 0xC000
2078 
2079 #define R_AX_CMAC_FUNC_EN 0xC000
2080 #define R_AX_CMAC_FUNC_EN_C1 0xE000
2081 #define B_AX_CMAC_CRPRT BIT(31)
2082 #define B_AX_CMAC_EN BIT(30)
2083 #define B_AX_CMAC_TXEN BIT(29)
2084 #define B_AX_CMAC_RXEN BIT(28)
2085 #define B_AX_FORCE_CMACREG_GCKEN BIT(15)
2086 #define B_AX_PHYINTF_EN BIT(5)
2087 #define B_AX_CMAC_DMA_EN BIT(4)
2088 #define B_AX_PTCLTOP_EN BIT(3)
2089 #define B_AX_SCHEDULER_EN BIT(2)
2090 #define B_AX_TMAC_EN BIT(1)
2091 #define B_AX_RMAC_EN BIT(0)
2092 
2093 #define R_AX_CK_EN 0xC004
2094 #define R_AX_CK_EN_C1 0xE004
2095 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2096 #define B_AX_CMAC_CKEN BIT(30)
2097 #define B_AX_PHYINTF_CKEN BIT(5)
2098 #define B_AX_CMAC_DMA_CKEN BIT(4)
2099 #define B_AX_PTCLTOP_CKEN BIT(3)
2100 #define B_AX_SCHEDULER_CKEN BIT(2)
2101 #define B_AX_TMAC_CKEN BIT(1)
2102 #define B_AX_RMAC_CKEN BIT(0)
2103 
2104 #define R_AX_WMAC_RFMOD 0xC010
2105 #define R_AX_WMAC_RFMOD_C1 0xE010
2106 #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
2107 #define AX_WMAC_RFMOD_20M 0
2108 #define AX_WMAC_RFMOD_40M 1
2109 #define AX_WMAC_RFMOD_80M 2
2110 #define AX_WMAC_RFMOD_160M 3
2111 
2112 #define R_AX_GID_POSITION0 0xC070
2113 #define R_AX_GID_POSITION0_C1 0xE070
2114 #define R_AX_GID_POSITION1 0xC074
2115 #define R_AX_GID_POSITION1_C1 0xE074
2116 #define R_AX_GID_POSITION2 0xC078
2117 #define R_AX_GID_POSITION2_C1 0xE078
2118 #define R_AX_GID_POSITION3 0xC07C
2119 #define R_AX_GID_POSITION3_C1 0xE07C
2120 #define R_AX_GID_POSITION_EN0 0xC080
2121 #define R_AX_GID_POSITION_EN0_C1 0xE080
2122 #define R_AX_GID_POSITION_EN1 0xC084
2123 #define R_AX_GID_POSITION_EN1_C1 0xE084
2124 
2125 #define R_AX_TX_SUB_CARRIER_VALUE 0xC088
2126 #define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088
2127 #define B_AX_TXSC_80M_MASK GENMASK(11, 8)
2128 #define B_AX_TXSC_40M_MASK GENMASK(7, 4)
2129 #define B_AX_TXSC_20M_MASK GENMASK(3, 0)
2130 
2131 #define R_AX_PTCL_RRSR1 0xC090
2132 #define R_AX_PTCL_RRSR1_C1 0xE090
2133 #define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8)
2134 #define RRSR_OFDM_CCK_EN 3
2135 #define B_AX_RSC_MASK GENMASK(7, 6)
2136 #define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
2137 
2138 #define R_AX_CMAC_ERR_IMR 0xC160
2139 #define R_AX_CMAC_ERR_IMR_C1 0xE160
2140 #define B_AX_WMAC_TX_ERR_IND_EN BIT(7)
2141 #define B_AX_WMAC_RX_ERR_IND_EN BIT(6)
2142 #define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5)
2143 #define B_AX_PHYINTF_ERR_IND_EN BIT(4)
2144 #define B_AX_DMA_TOP_ERR_IND_EN BIT(3)
2145 #define B_AX_PTCL_TOP_ERR_IND_EN BIT(1)
2146 #define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0)
2147 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2148 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2149 #define CMAC0_ERR_IMR_DIS 0
2150 #define CMAC1_ERR_IMR_DIS 0
2151 
2152 #define R_AX_CMAC_ERR_ISR 0xC164
2153 #define R_AX_CMAC_ERR_ISR_C1 0xE164
2154 #define B_AX_WMAC_TX_ERR_IND BIT(7)
2155 #define B_AX_WMAC_RX_ERR_IND BIT(6)
2156 #define B_AX_TXPWR_CTRL_ERR_IND BIT(5)
2157 #define B_AX_PHYINTF_ERR_IND BIT(4)
2158 #define B_AX_DMA_TOP_ERR_IND BIT(3)
2159 #define B_AX_PTCL_TOP_ERR_IND BIT(1)
2160 #define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
2161 
2162 #define R_AX_PORT0_TSF_SYNC 0xC2A0
2163 #define R_AX_PORT0_TSF_SYNC_C1 0xE2A0
2164 #define R_AX_PORT1_TSF_SYNC 0xC2A4
2165 #define R_AX_PORT1_TSF_SYNC_C1 0xE2A4
2166 #define R_AX_PORT2_TSF_SYNC 0xC2A8
2167 #define R_AX_PORT2_TSF_SYNC_C1 0xE2A8
2168 #define R_AX_PORT3_TSF_SYNC 0xC2AC
2169 #define R_AX_PORT3_TSF_SYNC_C1 0xE2AC
2170 #define R_AX_PORT4_TSF_SYNC 0xC2B0
2171 #define R_AX_PORT4_TSF_SYNC_C1 0xE2B0
2172 #define B_AX_SYNC_NOW BIT(30)
2173 #define B_AX_SYNC_ONCE BIT(29)
2174 #define B_AX_SYNC_AUTO BIT(28)
2175 #define B_AX_SYNC_PORT_SRC GENMASK(26, 24)
2176 #define B_AX_SYNC_PORT_OFFSET_SIGN BIT(18)
2177 #define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)
2178 
2179 #define R_AX_MACID_SLEEP_0 0xC2C0
2180 #define R_AX_MACID_SLEEP_0_C1 0xE2C0
2181 #define B_AX_MACID31_0_SLEEP_SH 0
2182 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2183 
2184 #define R_AX_MACID_SLEEP_1 0xC2C4
2185 #define R_AX_MACID_SLEEP_1_C1 0xE2C4
2186 #define B_AX_MACID63_32_SLEEP_SH 0
2187 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2188 
2189 #define R_AX_MACID_SLEEP_2 0xC2C8
2190 #define R_AX_MACID_SLEEP_2_C1 0xE2C8
2191 #define B_AX_MACID95_64_SLEEP_SH 0
2192 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2193 
2194 #define R_AX_MACID_SLEEP_3 0xC2CC
2195 #define R_AX_MACID_SLEEP_3_C1 0xE2CC
2196 #define B_AX_MACID127_96_SLEEP_SH 0
2197 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2198 
2199 #define SCH_PREBKF_24US 0x18
2200 #define R_AX_PREBKF_CFG_0 0xC338
2201 #define R_AX_PREBKF_CFG_0_C1 0xE338
2202 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
2203 
2204 #define R_AX_PREBKF_CFG_1 0xC33C
2205 #define R_AX_PREBKF_CFG_1_C1 0xE33C
2206 #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
2207 #define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)
2208 #define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
2209 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
2210 #define SIFS_MACTXEN_T1 0x47
2211 #define SIFS_MACTXEN_T1_V1 0x41
2212 
2213 #define R_AX_CCA_CFG_0 0xC340
2214 #define R_AX_CCA_CFG_0_C1 0xE340
2215 #define B_AX_BTCCA_BRK_TXOP_EN BIT(9)
2216 #define B_AX_BTCCA_EN BIT(5)
2217 #define B_AX_EDCCA_EN BIT(4)
2218 #define B_AX_SEC80_EN BIT(3)
2219 #define B_AX_SEC40_EN BIT(2)
2220 #define B_AX_SEC20_EN BIT(1)
2221 #define B_AX_CCA_EN BIT(0)
2222 
2223 #define R_AX_CTN_TXEN 0xC348
2224 #define R_AX_CTN_TXEN_C1 0xE348
2225 #define B_AX_CTN_TXEN_TWT_1 BIT(15)
2226 #define B_AX_CTN_TXEN_TWT_0 BIT(14)
2227 #define B_AX_CTN_TXEN_ULQ BIT(13)
2228 #define B_AX_CTN_TXEN_BCNQ BIT(12)
2229 #define B_AX_CTN_TXEN_HGQ BIT(11)
2230 #define B_AX_CTN_TXEN_CPUMGQ BIT(10)
2231 #define B_AX_CTN_TXEN_MGQ1 BIT(9)
2232 #define B_AX_CTN_TXEN_MGQ BIT(8)
2233 #define B_AX_CTN_TXEN_VO_1 BIT(7)
2234 #define B_AX_CTN_TXEN_VI_1 BIT(6)
2235 #define B_AX_CTN_TXEN_BK_1 BIT(5)
2236 #define B_AX_CTN_TXEN_BE_1 BIT(4)
2237 #define B_AX_CTN_TXEN_VO_0 BIT(3)
2238 #define B_AX_CTN_TXEN_VI_0 BIT(2)
2239 #define B_AX_CTN_TXEN_BK_0 BIT(1)
2240 #define B_AX_CTN_TXEN_BE_0 BIT(0)
2241 #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
2242 
2243 #define R_AX_MUEDCA_BE_PARAM_0 0xC350
2244 #define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350
2245 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
2246 #define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8)
2247 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
2248 
2249 #define R_AX_MUEDCA_BK_PARAM_0 0xC354
2250 #define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354
2251 #define R_AX_MUEDCA_VI_PARAM_0 0xC358
2252 #define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358
2253 #define R_AX_MUEDCA_VO_PARAM_0 0xC35C
2254 #define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C
2255 
2256 #define R_AX_MUEDCA_EN 0xC370
2257 #define R_AX_MUEDCA_EN_C1 0xE370
2258 #define B_AX_MUEDCA_WMM_SEL BIT(8)
2259 #define B_AX_SET_MUEDCATIMER_TF_0 BIT(4)
2260 #define B_AX_MUEDCA_EN_0 BIT(0)
2261 
2262 #define R_AX_CCA_CONTROL 0xC390
2263 #define R_AX_CCA_CONTROL_C1 0xE390
2264 #define B_AX_TB_CHK_TX_NAV BIT(31)
2265 #define B_AX_TB_CHK_BASIC_NAV BIT(30)
2266 #define B_AX_TB_CHK_BTCCA BIT(29)
2267 #define B_AX_TB_CHK_EDCCA BIT(28)
2268 #define B_AX_TB_CHK_CCA_S80 BIT(27)
2269 #define B_AX_TB_CHK_CCA_S40 BIT(26)
2270 #define B_AX_TB_CHK_CCA_S20 BIT(25)
2271 #define B_AX_TB_CHK_CCA_P20 BIT(24)
2272 #define B_AX_SIFS_CHK_BTCCA BIT(21)
2273 #define B_AX_SIFS_CHK_EDCCA BIT(20)
2274 #define B_AX_SIFS_CHK_CCA_S80 BIT(19)
2275 #define B_AX_SIFS_CHK_CCA_S40 BIT(18)
2276 #define B_AX_SIFS_CHK_CCA_S20 BIT(17)
2277 #define B_AX_SIFS_CHK_CCA_P20 BIT(16)
2278 #define B_AX_CTN_CHK_TXNAV BIT(8)
2279 #define B_AX_CTN_CHK_INTRA_NAV BIT(7)
2280 #define B_AX_CTN_CHK_BASIC_NAV BIT(6)
2281 #define B_AX_CTN_CHK_BTCCA BIT(5)
2282 #define B_AX_CTN_CHK_EDCCA BIT(4)
2283 #define B_AX_CTN_CHK_CCA_S80 BIT(3)
2284 #define B_AX_CTN_CHK_CCA_S40 BIT(2)
2285 #define B_AX_CTN_CHK_CCA_S20 BIT(1)
2286 #define B_AX_CTN_CHK_CCA_P20 BIT(0)
2287 
2288 #define R_AX_CTN_DRV_TXEN 0xC398
2289 #define R_AX_CTN_DRV_TXEN_C1 0xE398
2290 #define B_AX_CTN_TXEN_TWT_3 BIT(17)
2291 #define B_AX_CTN_TXEN_TWT_2 BIT(16)
2292 #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
2293 
2294 #define R_AX_SCHEDULE_ERR_IMR 0xC3E8
2295 #define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8
2296 #define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1)
2297 
2298 #define R_AX_SCHEDULE_ERR_ISR 0xC3EC
2299 #define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC
2300 
2301 #define R_AX_SCH_DBG_SEL 0xC3F4
2302 #define R_AX_SCH_DBG_SEL_C1 0xE3F4
2303 #define B_AX_SCH_DBG_EN BIT(16)
2304 #define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8)
2305 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
2306 
2307 #define R_AX_SCH_DBG 0xC3F8
2308 #define R_AX_SCH_DBG_C1 0xE3F8
2309 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2310 
2311 #define R_AX_SCH_EXT_CTRL 0xC3FC
2312 #define R_AX_SCH_EXT_CTRL_C1 0xE3FC
2313 #define B_AX_PORT_RST_TSF_ADV BIT(1)
2314 
2315 #define R_AX_PORT_CFG_P0 0xC400
2316 #define R_AX_PORT_CFG_P1 0xC440
2317 #define R_AX_PORT_CFG_P2 0xC480
2318 #define R_AX_PORT_CFG_P3 0xC4C0
2319 #define R_AX_PORT_CFG_P4 0xC500
2320 #define B_AX_BRK_SETUP BIT(16)
2321 #define B_AX_TBTT_UPD_SHIFT_SEL BIT(15)
2322 #define B_AX_BCN_DROP_ALLOW BIT(14)
2323 #define B_AX_TBTT_PROHIB_EN BIT(13)
2324 #define B_AX_BCNTX_EN BIT(12)
2325 #define B_AX_NET_TYPE_MASK GENMASK(11, 10)
2326 #define B_AX_BCN_FORCETX_EN BIT(9)
2327 #define B_AX_TXBCN_BTCCA_EN BIT(8)
2328 #define B_AX_BCNERR_CNT_EN BIT(7)
2329 #define B_AX_BCN_AGRES BIT(6)
2330 #define B_AX_TSFTR_RST BIT(5)
2331 #define B_AX_RX_BSSID_FIT_EN BIT(4)
2332 #define B_AX_TSF_UDT_EN BIT(3)
2333 #define B_AX_PORT_FUNC_EN BIT(2)
2334 #define B_AX_TXBCN_RPT_EN BIT(1)
2335 #define B_AX_RXBCN_RPT_EN BIT(0)
2336 
2337 #define R_AX_TBTT_PROHIB_P0 0xC404
2338 #define R_AX_TBTT_PROHIB_P1 0xC444
2339 #define R_AX_TBTT_PROHIB_P2 0xC484
2340 #define R_AX_TBTT_PROHIB_P3 0xC4C4
2341 #define R_AX_TBTT_PROHIB_P4 0xC504
2342 #define B_AX_TBTT_HOLD_MASK GENMASK(27, 16)
2343 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2344 
2345 #define R_AX_BCN_AREA_P0 0xC408
2346 #define R_AX_BCN_AREA_P1 0xC448
2347 #define R_AX_BCN_AREA_P2 0xC488
2348 #define R_AX_BCN_AREA_P3 0xC4C8
2349 #define R_AX_BCN_AREA_P4 0xC508
2350 #define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16)
2351 #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
2352 
2353 #define R_AX_BCNERLYINT_CFG_P0 0xC40C
2354 #define R_AX_BCNERLYINT_CFG_P1 0xC44C
2355 #define R_AX_BCNERLYINT_CFG_P2 0xC48C
2356 #define R_AX_BCNERLYINT_CFG_P3 0xC4CC
2357 #define R_AX_BCNERLYINT_CFG_P4 0xC50C
2358 #define B_AX_BCNERLY_MASK GENMASK(11, 0)
2359 
2360 #define R_AX_TBTTERLYINT_CFG_P0 0xC40E
2361 #define R_AX_TBTTERLYINT_CFG_P1 0xC44E
2362 #define R_AX_TBTTERLYINT_CFG_P2 0xC48E
2363 #define R_AX_TBTTERLYINT_CFG_P3 0xC4CE
2364 #define R_AX_TBTTERLYINT_CFG_P4 0xC50E
2365 #define B_AX_TBTTERLY_MASK GENMASK(11, 0)
2366 
2367 #define R_AX_TBTT_AGG_P0 0xC412
2368 #define R_AX_TBTT_AGG_P1 0xC452
2369 #define R_AX_TBTT_AGG_P2 0xC492
2370 #define R_AX_TBTT_AGG_P3 0xC4D2
2371 #define R_AX_TBTT_AGG_P4 0xC512
2372 #define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8)
2373 
2374 #define R_AX_BCN_SPACE_CFG_P0 0xC414
2375 #define R_AX_BCN_SPACE_CFG_P1 0xC454
2376 #define R_AX_BCN_SPACE_CFG_P2 0xC494
2377 #define R_AX_BCN_SPACE_CFG_P3 0xC4D4
2378 #define R_AX_BCN_SPACE_CFG_P4 0xC514
2379 #define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16)
2380 #define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
2381 
2382 #define R_AX_BCN_FORCETX_P0 0xC418
2383 #define R_AX_BCN_FORCETX_P1 0xC458
2384 #define R_AX_BCN_FORCETX_P2 0xC498
2385 #define R_AX_BCN_FORCETX_P3 0xC4D8
2386 #define R_AX_BCN_FORCETX_P4 0xC518
2387 #define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16)
2388 #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
2389 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2390 
2391 #define R_AX_BCN_ERR_CNT_P0 0xC420
2392 #define R_AX_BCN_ERR_CNT_P1 0xC460
2393 #define R_AX_BCN_ERR_CNT_P2 0xC4A0
2394 #define R_AX_BCN_ERR_CNT_P3 0xC4E0
2395 #define R_AX_BCN_ERR_CNT_P4 0xC520
2396 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2397 #define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16)
2398 #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
2399 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2400 
2401 #define R_AX_BCN_ERR_FLAG_P0 0xC424
2402 #define R_AX_BCN_ERR_FLAG_P1 0xC464
2403 #define R_AX_BCN_ERR_FLAG_P2 0xC4A4
2404 #define R_AX_BCN_ERR_FLAG_P3 0xC4E4
2405 #define R_AX_BCN_ERR_FLAG_P4 0xC524
2406 #define B_AX_BCN_ERR_FLAG_OTHERS BIT(6)
2407 #define B_AX_BCN_ERR_FLAG_MAC BIT(5)
2408 #define B_AX_BCN_ERR_FLAG_TXON BIT(4)
2409 #define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3)
2410 #define B_AX_BCN_ERR_FLAG_INVALID BIT(2)
2411 #define B_AX_BCN_ERR_FLAG_CMP BIT(1)
2412 #define B_AX_BCN_ERR_FLAG_LOCK BIT(0)
2413 
2414 #define R_AX_DTIM_CTRL_P0 0xC426
2415 #define R_AX_DTIM_CTRL_P1 0xC466
2416 #define R_AX_DTIM_CTRL_P2 0xC4A6
2417 #define R_AX_DTIM_CTRL_P3 0xC4E6
2418 #define R_AX_DTIM_CTRL_P4 0xC526
2419 #define B_AX_DTIM_NUM_MASK GENMASK(15, 8)
2420 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2421 
2422 #define R_AX_TBTT_SHIFT_P0 0xC428
2423 #define R_AX_TBTT_SHIFT_P1 0xC468
2424 #define R_AX_TBTT_SHIFT_P2 0xC4A8
2425 #define R_AX_TBTT_SHIFT_P3 0xC4E8
2426 #define R_AX_TBTT_SHIFT_P4 0xC528
2427 #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
2428 #define B_AX_TBTT_SHIFT_OFST_SIGN BIT(11)
2429 #define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0)
2430 
2431 #define R_AX_BCN_CNT_TMR_P0 0xC434
2432 #define R_AX_BCN_CNT_TMR_P1 0xC474
2433 #define R_AX_BCN_CNT_TMR_P2 0xC4B4
2434 #define R_AX_BCN_CNT_TMR_P3 0xC4F4
2435 #define R_AX_BCN_CNT_TMR_P4 0xC534
2436 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2437 
2438 #define R_AX_TSFTR_LOW_P0 0xC438
2439 #define R_AX_TSFTR_LOW_P1 0xC478
2440 #define R_AX_TSFTR_LOW_P2 0xC4B8
2441 #define R_AX_TSFTR_LOW_P3 0xC4F8
2442 #define R_AX_TSFTR_LOW_P4 0xC538
2443 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2444 
2445 #define R_AX_TSFTR_HIGH_P0 0xC43C
2446 #define R_AX_TSFTR_HIGH_P1 0xC47C
2447 #define R_AX_TSFTR_HIGH_P2 0xC4BC
2448 #define R_AX_TSFTR_HIGH_P3 0xC4FC
2449 #define R_AX_TSFTR_HIGH_P4 0xC53C
2450 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2451 
2452 #define R_AX_BCN_DROP_ALL0 0xC560
2453 #define R_AX_BCN_DROP_ALL0_C1 0xE560
2454 #define B_AX_BCN_DROP_ALL_P4 BIT(4)
2455 #define B_AX_BCN_DROP_ALL_P3 BIT(3)
2456 #define B_AX_BCN_DROP_ALL_P2 BIT(2)
2457 #define B_AX_BCN_DROP_ALL_P1 BIT(1)
2458 #define B_AX_BCN_DROP_ALL_P0 BIT(0)
2459 
2460 #define R_AX_MBSSID_CTRL 0xC568
2461 #define R_AX_MBSSID_CTRL_C1 0xE568
2462 #define B_AX_P0MB_ALL_MASK GENMASK(23, 1)
2463 #define B_AX_P0MB_NUM_MASK GENMASK(19, 16)
2464 #define B_AX_P0MB15_EN BIT(15)
2465 #define B_AX_P0MB14_EN BIT(14)
2466 #define B_AX_P0MB13_EN BIT(13)
2467 #define B_AX_P0MB12_EN BIT(12)
2468 #define B_AX_P0MB11_EN BIT(11)
2469 #define B_AX_P0MB10_EN BIT(10)
2470 #define B_AX_P0MB9_EN BIT(9)
2471 #define B_AX_P0MB8_EN BIT(8)
2472 #define B_AX_P0MB7_EN BIT(7)
2473 #define B_AX_P0MB6_EN BIT(6)
2474 #define B_AX_P0MB5_EN BIT(5)
2475 #define B_AX_P0MB4_EN BIT(4)
2476 #define B_AX_P0MB3_EN BIT(3)
2477 #define B_AX_P0MB2_EN BIT(2)
2478 #define B_AX_P0MB1_EN BIT(1)
2479 
2480 #define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590
2481 #define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590
2482 #define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
2483 #define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
2484 
2485 #define R_AX_PTCL_COMMON_SETTING_0 0xC600
2486 #define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600
2487 #define B_AX_PCIE_MODE_MASK GENMASK(15, 14)
2488 #define B_AX_CPUMGQ_LIFETIME_EN BIT(8)
2489 #define B_AX_MGQ_LIFETIME_EN BIT(7)
2490 #define B_AX_LIFETIME_EN BIT(6)
2491 #define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4)
2492 #define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3)
2493 #define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2)
2494 #define B_AX_CMAC_TX_MODE_1 BIT(1)
2495 #define B_AX_CMAC_TX_MODE_0 BIT(0)
2496 
2497 #define R_AX_AMPDU_AGG_LIMIT 0xC610
2498 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2499 #define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
2500 #define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
2501 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2502 
2503 #define R_AX_AGG_LEN_HT_0 0xC614
2504 #define R_AX_AGG_LEN_HT_0_C1 0xE614
2505 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2506 #define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8)
2507 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2508 
2509 #define R_AX_AGG_LEN_VHT_0 0xC618
2510 #define R_AX_AGG_LEN_VHT_0_C1 0xE618
2511 #define B_AX_AMPDU_MAX_LEN_VHT_MASK GENMASK(19, 0)
2512 
2513 #define S_AX_CTS2S_TH_SEC_256B 1
2514 #define R_AX_SIFS_SETTING 0xC624
2515 #define R_AX_SIFS_SETTING_C1 0xE624
2516 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2517 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
2518 #define B_AX_HW_CTS2SELF_EN BIT(16)
2519 #define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8
2520 #define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
2521 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2522 #define S_AX_CTS2S_TH_1K 4
2523 
2524 #define R_AX_TXRATE_CHK 0xC628
2525 #define R_AX_TXRATE_CHK_C1 0xE628
2526 #define B_AX_DEFT_RATE_MASK GENMASK(15, 7)
2527 #define B_AX_BAND_MODE BIT(4)
2528 #define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)
2529 #define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1)
2530 #define B_AX_CHECK_CCK_EN BIT(0)
2531 
2532 #define R_AX_TXCNT 0xC62C
2533 #define R_AX_TXCNT_C1 0xE62C
2534 #define B_AX_ADD_TXCNT_BY BIT(31)
2535 #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
2536 #define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16)
2537 
2538 #define R_AX_MBSSID_DROP_0 0xC63C
2539 #define R_AX_MBSSID_DROP_0_C1 0xE63C
2540 #define B_AX_GI_LTF_FB_SEL BIT(30)
2541 #define B_AX_RATE_SEL_MASK GENMASK(29, 24)
2542 #define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)
2543 #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
2544 
2545 #define R_AX_PTCLRPT_FULL_HDL 0xC660
2546 #define R_AX_PTCLRPT_FULL_HDL_C1 0xE660
2547 #define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)
2548 #define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9)
2549 #define B_AX_F2PCMD_RPT_EN BIT(8)
2550 #define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
2551 #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
2552 #define FWD_TO_WLCPU 1
2553 #define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
2554 #define B_AX_F2PCMDRPT_FULL_DROP BIT(1)
2555 #define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0)
2556 
2557 #define R_AX_BT_PLT 0xC67C
2558 #define R_AX_BT_PLT_C1 0xE67C
2559 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2560 #define B_AX_BT_PLT_RST BIT(9)
2561 #define B_AX_PLT_EN BIT(8)
2562 #define B_AX_RX_PLT_GNT_LTE_RX BIT(7)
2563 #define B_AX_RX_PLT_GNT_BT_RX BIT(6)
2564 #define B_AX_RX_PLT_GNT_BT_TX BIT(5)
2565 #define B_AX_RX_PLT_GNT_WL BIT(4)
2566 #define B_AX_TX_PLT_GNT_LTE_RX BIT(3)
2567 #define B_AX_TX_PLT_GNT_BT_RX BIT(2)
2568 #define B_AX_TX_PLT_GNT_BT_TX BIT(1)
2569 #define B_AX_TX_PLT_GNT_WL BIT(0)
2570 
2571 #define R_AX_PTCL_BSS_COLOR_0 0xC6A0
2572 #define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0
2573 #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
2574 #define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16)
2575 #define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8)
2576 #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
2577 
2578 #define R_AX_PTCL_BSS_COLOR_1 0xC6A4
2579 #define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4
2580 #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
2581 
2582 #define R_AX_PTCL_IMR0 0xC6C0
2583 #define R_AX_PTCL_IMR0_C1 0xE6C0
2584 #define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
2585 #define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30)
2586 #define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29)
2587 #define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28)
2588 #define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27)
2589 #define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26)
2590 #define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25)
2591 #define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24)
2592 #define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23)
2593 #define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15)
2594 #define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14)
2595 #define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12)
2596 #define B_AX_Q_PKTID_ERR_INT_EN BIT(11)
2597 #define B_AX_D_PKTID_ERR_INT_EN BIT(10)
2598 #define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9)
2599 #define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8)
2600 #define B_AX_FSM1_TIMEOUT_ERR_INT_EN BIT(1)
2601 #define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
2602 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2603 #define B_AX_PTCL_IMR_CLR (B_AX_FSM_TIMEOUT_ERR_INT_EN | \
2604 			   B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | \
2605 			   B_AX_TXPRT_FULL_DROP_ERR_INT_EN | \
2606 			   B_AX_D_PKTID_ERR_INT_EN | \
2607 			   B_AX_Q_PKTID_ERR_INT_EN | \
2608 			   B_AX_BCNQ_ORDER_ERR_INT_EN | \
2609 			   B_AX_TWTSP_QSEL_ERR_INT_EN | \
2610 			   B_AX_F2PCMD_EMPTY_ERR_INT_EN | \
2611 			   B_AX_TX_RECORD_PKTID_ERR_INT_EN | \
2612 			   B_AX_TX_SPF_U3_PKTID_ERR_INT_EN | \
2613 			   B_AX_TX_SPF_U2_PKTID_ERR_INT_EN | \
2614 			   B_AX_TX_SPF_U1_PKTID_ERR_INT_EN | \
2615 			   B_AX_RX_SPF_U0_PKTID_ERR_INT_EN | \
2616 			   B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | \
2617 			   B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN | \
2618 			   B_AX_F2PCMD_RD_PKTID_ERR_INT_EN | \
2619 			   B_AX_F2PCMD_PKTID_ERR_INT_EN)
2620 #define B_AX_PTCL_IMR_SET (B_AX_FSM_TIMEOUT_ERR_INT_EN | \
2621 			   B_AX_TX_RECORD_PKTID_ERR_INT_EN | \
2622 			   B_AX_F2PCMD_USER_ALLC_ERR_INT_EN)
2623 #define B_AX_PTCL_IMR_CLR_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \
2624 			      B_AX_FSM_TIMEOUT_ERR_INT_EN)
2625 #define B_AX_PTCL_IMR_SET_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \
2626 			      B_AX_FSM_TIMEOUT_ERR_INT_EN)
2627 
2628 #define R_AX_PTCL_ISR0 0xC6C4
2629 #define R_AX_PTCL_ISR0_C1 0xE6C4
2630 
2631 #define S_AX_PTCL_TO_2MS 0x3F
2632 #define R_AX_PTCL_FSM_MON 0xC6E8
2633 #define R_AX_PTCL_FSM_MON_C1 0xE6E8
2634 #define B_AX_PTCL_TX_ARB_TO_MODE BIT(6)
2635 #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
2636 
2637 #define R_AX_PTCL_TX_CTN_SEL 0xC6EC
2638 #define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC
2639 #define B_AX_PTCL_TX_ON_STAT BIT(7)
2640 
2641 #define R_AX_PTCL_DBG_INFO 0xC6F0
2642 #define R_AX_PTCL_DBG_INFO_C1 0xE6F0
2643 #define B_AX_PTCL_DBG_INFO_MASK_BY_PORT(port) \
2644 ({\
2645 	typeof(port) _port = (port); \
2646 	GENMASK((_port) * 2 + 1, (_port) * 2); \
2647 })
2648 
2649 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2650 #define R_AX_PTCL_DBG 0xC6F4
2651 #define R_AX_PTCL_DBG_C1 0xE6F4
2652 #define B_AX_PTCL_DBG_EN BIT(8)
2653 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2654 #define AX_PTCL_DBG_BCNQ_NUM0 8
2655 #define AX_PTCL_DBG_BCNQ_NUM1 9
2656 
2657 
2658 #define R_AX_DLE_CTRL 0xC800
2659 #define R_AX_DLE_CTRL_C1 0xE800
2660 #define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23)
2661 #define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15)
2662 #define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14)
2663 #define B_AX_DLE_IMR_CLR (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
2664 			  B_AX_RXDATA_FSM_HANG_ERROR_IMR | \
2665 			  B_AX_NO_RESERVE_PAGE_ERR_IMR)
2666 #define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
2667 			  B_AX_RXDATA_FSM_HANG_ERROR_IMR)
2668 
2669 #define R_AX_RX_ERR_FLAG 0xC800
2670 #define R_AX_RX_ERR_FLAG_C1 0xE800
2671 #define B_AX_RX_GET_NO_PAGE_ERR BIT(31)
2672 #define B_AX_RX_GET_NULL_PKT_ERR BIT(30)
2673 #define B_AX_RX_RU0_FSM_HANG_ERR BIT(29)
2674 #define B_AX_RX_RU1_FSM_HANG_ERR BIT(28)
2675 #define B_AX_RX_RU2_FSM_HANG_ERR BIT(27)
2676 #define B_AX_RX_RU3_FSM_HANG_ERR BIT(26)
2677 #define B_AX_RX_RU4_FSM_HANG_ERR BIT(25)
2678 #define B_AX_RX_RU5_FSM_HANG_ERR BIT(24)
2679 #define B_AX_RX_RU6_FSM_HANG_ERR BIT(23)
2680 #define B_AX_RX_RU7_FSM_HANG_ERR BIT(22)
2681 #define B_AX_RX_RXSTS_FSM_HANG_ERR BIT(21)
2682 #define B_AX_RX_CSI_FSM_HANG_ERR BIT(20)
2683 #define B_AX_RX_TXRPT_FSM_HANG_ERR BIT(19)
2684 #define B_AX_RX_F2PCMD_FSM_HANG_ERR BIT(18)
2685 #define B_AX_RX_RU0_ZERO_LEN_ERR BIT(17)
2686 #define B_AX_RX_RU1_ZERO_LEN_ERR BIT(16)
2687 #define B_AX_RX_RU2_ZERO_LEN_ERR BIT(15)
2688 #define B_AX_RX_RU3_ZERO_LEN_ERR BIT(14)
2689 #define B_AX_RX_RU4_ZERO_LEN_ERR BIT(13)
2690 #define B_AX_RX_RU5_ZERO_LEN_ERR BIT(12)
2691 #define B_AX_RX_RU6_ZERO_LEN_ERR BIT(11)
2692 #define B_AX_RX_RU7_ZERO_LEN_ERR BIT(10)
2693 #define B_AX_RX_RXSTS_ZERO_LEN_ERR BIT(9)
2694 #define B_AX_RX_CSI_ZERO_LEN_ERR BIT(8)
2695 #define B_AX_PLE_DATA_OPT_FSM_HANG BIT(7)
2696 #define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG BIT(6)
2697 #define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG BIT(5)
2698 #define B_AX_PLE_WD_OPT_FSM_HANG BIT(4)
2699 #define B_AX_PLE_ENQ_FSM_HANG BIT(3)
2700 #define B_AX_RXDATA_ENQUE_ORDER_ERR BIT(2)
2701 #define B_AX_RXSTS_ENQUE_ORDER_ERR BIT(1)
2702 #define B_AX_RX_CSI_PKT_NUM_ERR BIT(0)
2703 
2704 #define R_AX_RXDMA_CTRL_0 0xC804
2705 #define R_AX_RXDMA_CTRL_0_C1 0xE804
2706 #define B_AX_RXDMA_DBGOUT_EN BIT(31)
2707 #define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29)
2708 #define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25)
2709 #define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21)
2710 #define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19)
2711 #define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13)
2712 #define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10)
2713 #define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9)
2714 #define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7)
2715 #define B_AX_RXDMA_DIS_CSI_WAIT_PTR_CLR BIT(6)
2716 #define B_AX_RXSTS_PTR_FULL_MODE BIT(5)
2717 #define B_AX_CSI_PTR_FULL_MODE BIT(4)
2718 #define B_AX_RU3_PTR_FULL_MODE BIT(3)
2719 #define B_AX_RU2_PTR_FULL_MODE BIT(2)
2720 #define B_AX_RU1_PTR_FULL_MODE BIT(1)
2721 #define B_AX_RU0_PTR_FULL_MODE BIT(0)
2722 #define RX_FULL_MODE (B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE | \
2723 		      B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \
2724 		      B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE)
2725 
2726 #define R_AX_RX_CTRL0 0xC808
2727 #define R_AX_RX_CTRL0_C1 0xE808
2728 #define B_AX_DLE_CLOCK_FORCE_V1 BIT(31)
2729 #define B_AX_TXDMA_CLOCK_FORCE_V1 BIT(30)
2730 #define B_AX_RXDMA_CLOCK_FORCE_V1 BIT(29)
2731 #define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24)
2732 #define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18)
2733 #define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15)
2734 #define B_AX_RXDMA_DIS_CSI_RELEASE_V1 BIT(14)
2735 #define B_AX_CSI_PTR_FULL_MODE_V1 BIT(13)
2736 #define B_AX_RXDATA_PTR_FULL_MODE BIT(12)
2737 #define B_AX_RXSTS_PTR_FULL_MODE_V1 BIT(11)
2738 #define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8)
2739 #define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5)
2740 #define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)
2741 #define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)
2742 
2743 #define R_AX_RX_CTRL1 0xC80C
2744 #define R_AX_RX_CTRL1_C1 0xE80C
2745 #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31)
2746 #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25)
2747 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_EN BIT(24)
2748 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18)
2749 #define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_EN BIT(17)
2750 #define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11)
2751 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_EN BIT(10)
2752 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
2753 #define B_AX_ORDER_FIFO_OUT BIT(3)
2754 #define B_AX_ORDER_FIFO_EMPTY BIT(2)
2755 #define B_AX_DBG_SEL_MASK GENMASK(1, 0)
2756 
2757 #define R_AX_RX_CTRL2 0xC810
2758 #define R_AX_RX_CTRL2_C1 0xE810
2759 #define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
2760 #define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28)
2761 #define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26)
2762 #define B_AX_DLE_ENQ_STATE_V1 BIT(25)
2763 #define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19)
2764 #define B_AX_MACRX_CS_MASK GENMASK(18, 14)
2765 #define B_AX_RXSTS_CS_MASK GENMASK(13, 9)
2766 #define B_AX_ERR_INDICATOR BIT(5)
2767 #define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
2768 
2769 #define R_AX_RXDMA_PKT_INFO_0 0xC814
2770 #define R_AX_RXDMA_PKT_INFO_1 0xC818
2771 #define R_AX_RXDMA_PKT_INFO_2 0xC81C
2772 
2773 #define R_AX_RX_ERR_FLAG_IMR 0xC804
2774 #define R_AX_RX_ERR_FLAG_IMR_C1 0xE804
2775 #define B_AX_RX_GET_NULL_PKT_ERR_MSK BIT(30)
2776 #define B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK BIT(29)
2777 #define B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK BIT(28)
2778 #define B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK BIT(27)
2779 #define B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK BIT(26)
2780 #define B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK BIT(25)
2781 #define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24)
2782 #define B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK BIT(23)
2783 #define B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK BIT(22)
2784 #define B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK BIT(21)
2785 #define B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK BIT(20)
2786 #define B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK BIT(19)
2787 #define B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK BIT(18)
2788 #define B_AX_RX_RU0_ZERO_LEN_ERR_MSK BIT(17)
2789 #define B_AX_RX_RU1_ZERO_LEN_ERR_MSK BIT(16)
2790 #define B_AX_RX_RU2_ZERO_LEN_ERR_MSK BIT(15)
2791 #define B_AX_RX_RU3_ZERO_LEN_ERR_MSK BIT(14)
2792 #define B_AX_RX_RU4_ZERO_LEN_ERR_MSK BIT(13)
2793 #define B_AX_RX_RU5_ZERO_LEN_ERR_MSK BIT(12)
2794 #define B_AX_RX_RU6_ZERO_LEN_ERR_MSK BIT(11)
2795 #define B_AX_RX_RU7_ZERO_LEN_ERR_MSK BIT(10)
2796 #define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9)
2797 #define B_AX_RX_CSI_ZERO_LEN_ERR_MSK BIT(8)
2798 #define B_AX_PLE_DATA_OPT_FSM_HANG_MSK BIT(7)
2799 #define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG_MSK BIT(6)
2800 #define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG_MSK BIT(5)
2801 #define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4)
2802 #define B_AX_PLE_ENQ_FSM_HANG_MSK BIT(3)
2803 #define B_AX_RXDATA_ENQUE_ORDER_ERR_MSK BIT(2)
2804 #define B_AX_RXSTS_ENQUE_ORDER_ERR_MSK BIT(1)
2805 #define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0)
2806 #define B_AX_RX_ERR_IMR_CLR_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \
2807 				B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \
2808 				B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \
2809 				B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \
2810 				B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \
2811 				B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \
2812 				B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \
2813 				B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \
2814 				B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \
2815 				B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \
2816 				B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \
2817 				B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \
2818 				B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \
2819 				B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \
2820 				B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \
2821 				B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \
2822 				B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \
2823 				B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \
2824 				B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \
2825 				B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \
2826 				B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \
2827 				B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \
2828 				B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \
2829 				B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \
2830 				B_AX_RX_GET_NULL_PKT_ERR_MSK)
2831 #define B_AX_RX_ERR_IMR_SET_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \
2832 				B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \
2833 				B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \
2834 				B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \
2835 				B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \
2836 				B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \
2837 				B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \
2838 				B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \
2839 				B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \
2840 				B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \
2841 				B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \
2842 				B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \
2843 				B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \
2844 				B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \
2845 				B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \
2846 				B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \
2847 				B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \
2848 				B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \
2849 				B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \
2850 				B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \
2851 				B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \
2852 				B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \
2853 				B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \
2854 				B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \
2855 				B_AX_RX_GET_NULL_PKT_ERR_MSK)
2856 
2857 #define R_AX_TX_ERR_FLAG_IMR 0xC870
2858 #define R_AX_TX_ERR_FLAG_IMR_C1 0xE870
2859 #define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31)
2860 #define B_AX_TX_RU1_FSM_HANG_ERR_MSK BIT(30)
2861 #define B_AX_TX_RU2_FSM_HANG_ERR_MSK BIT(29)
2862 #define B_AX_TX_RU3_FSM_HANG_ERR_MSK BIT(28)
2863 #define B_AX_TX_RU4_FSM_HANG_ERR_MSK BIT(27)
2864 #define B_AX_TX_RU5_FSM_HANG_ERR_MSK BIT(26)
2865 #define B_AX_TX_RU6_FSM_HANG_ERR_MSK BIT(25)
2866 #define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24)
2867 #define B_AX_TX_RU8_FSM_HANG_ERR_MSK BIT(23)
2868 #define B_AX_TX_RU9_FSM_HANG_ERR_MSK BIT(22)
2869 #define B_AX_TX_RU10_FSM_HANG_ERR_MSK BIT(21)
2870 #define B_AX_TX_RU11_FSM_HANG_ERR_MSK BIT(20)
2871 #define B_AX_TX_RU12_FSM_HANG_ERR_MSK BIT(19)
2872 #define B_AX_TX_RU13_FSM_HANG_ERR_MSK BIT(18)
2873 #define B_AX_TX_RU14_FSM_HANG_ERR_MSK BIT(17)
2874 #define B_AX_TX_RU15_FSM_HANG_ERR_MSK BIT(16)
2875 #define B_AX_TX_CSI_FSM_HANG_ERR_MSK BIT(15)
2876 #define B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK BIT(14)
2877 #define B_AX_TX_ERR_IMR_CLR_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \
2878 				B_AX_TX_CSI_FSM_HANG_ERR_MSK | \
2879 				B_AX_TX_RU7_FSM_HANG_ERR_MSK | \
2880 				B_AX_TX_RU6_FSM_HANG_ERR_MSK | \
2881 				B_AX_TX_RU5_FSM_HANG_ERR_MSK | \
2882 				B_AX_TX_RU4_FSM_HANG_ERR_MSK | \
2883 				B_AX_TX_RU3_FSM_HANG_ERR_MSK | \
2884 				B_AX_TX_RU2_FSM_HANG_ERR_MSK | \
2885 				B_AX_TX_RU1_FSM_HANG_ERR_MSK | \
2886 				B_AX_TX_RU0_FSM_HANG_ERR_MSK)
2887 #define B_AX_TX_ERR_IMR_SET_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \
2888 				B_AX_TX_CSI_FSM_HANG_ERR_MSK | \
2889 				B_AX_TX_RU7_FSM_HANG_ERR_MSK | \
2890 				B_AX_TX_RU6_FSM_HANG_ERR_MSK | \
2891 				B_AX_TX_RU5_FSM_HANG_ERR_MSK | \
2892 				B_AX_TX_RU4_FSM_HANG_ERR_MSK | \
2893 				B_AX_TX_RU3_FSM_HANG_ERR_MSK | \
2894 				B_AX_TX_RU2_FSM_HANG_ERR_MSK | \
2895 				B_AX_TX_RU1_FSM_HANG_ERR_MSK | \
2896 				B_AX_TX_RU0_FSM_HANG_ERR_MSK)
2897 
2898 #define R_AX_TCR0 0xCA00
2899 #define R_AX_TCR0_C1 0xEA00
2900 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2901 #define B_AX_TCR_UDF_EN BIT(23)
2902 #define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16)
2903 #define TCR_UDF_THSD 0x6
2904 #define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10)
2905 #define B_AX_TCR_VHTSIGA1_TXPS BIT(9)
2906 #define B_AX_TCR_PLCP_ERRHDL_EN BIT(8)
2907 #define B_AX_TCR_PADSEL BIT(7)
2908 #define B_AX_TCR_MASK_SIGBCRC BIT(6)
2909 #define B_AX_TCR_SR_VAL15_ALLOW BIT(5)
2910 #define B_AX_TCR_EN_EOF BIT(4)
2911 #define B_AX_TCR_EN_SCRAM_INC BIT(3)
2912 #define B_AX_TCR_EN_20MST BIT(2)
2913 #define B_AX_TCR_CRC BIT(1)
2914 #define B_AX_TCR_DISGCLK BIT(0)
2915 
2916 #define R_AX_TCR1 0xCA04
2917 #define R_AX_TCR1_C1 0xEA04
2918 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2919 #define B_AX_TCR_CCK_LOCK_CLK BIT(27)
2920 #define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26)
2921 #define B_AX_TCR_USTIME GENMASK(23, 16)
2922 #define B_AX_TCR_SMOOTH_VAL BIT(15)
2923 #define B_AX_TCR_SMOOTH_CTRL BIT(14)
2924 #define B_AX_CS_REQ_VAL BIT(13)
2925 #define B_AX_CS_REQ_SEL BIT(12)
2926 #define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)
2927 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2928 
2929 #define R_AX_MD_TSFT_STMP_CTL 0xCA08
2930 #define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08
2931 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2932 #define B_AX_STMP_THSD_MASK GENMASK(15, 8)
2933 #define B_AX_UPD_HGQMD BIT(1)
2934 #define B_AX_UPD_TIMIE BIT(0)
2935 
2936 #define R_AX_PPWRBIT_SETTING 0xCA0C
2937 #define R_AX_PPWRBIT_SETTING_C1 0xEA0C
2938 
2939 #define R_AX_TXD_FIFO_CTRL 0xCA1C
2940 #define R_AX_TXD_FIFO_CTRL_C1 0xEA1C
2941 #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
2942 #define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16)
2943 #define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12)
2944 #define TXDFIFO_HIGH_MCS_THRE 0x7
2945 #define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8)
2946 #define TXDFIFO_LOW_MCS_THRE  0x7
2947 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2948 #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
2949 
2950 #define R_AX_MACTX_DBG_SEL_CNT 0xCA20
2951 #define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20
2952 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2953 #define B_AX_MACTX_DMA_CNT GENMASK(23, 16)
2954 #define B_AX_LENGTH_ERR_FLAG_U3 BIT(11)
2955 #define B_AX_LENGTH_ERR_FLAG_U2 BIT(10)
2956 #define B_AX_LENGTH_ERR_FLAG_U1 BIT(9)
2957 #define B_AX_LENGTH_ERR_FLAG_U0 BIT(8)
2958 #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
2959 
2960 #define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4
2961 #define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4
2962 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2963 
2964 #define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8
2965 #define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8
2966 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2967 
2968 #define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC
2969 #define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC
2970 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2971 
2972 #define R_AX_RSP_CHK_SIG 0xCC00
2973 #define R_AX_RSP_CHK_SIG_C1 0xEC00
2974 #define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30)
2975 #define B_AX_RSP_TBPPDU_CHK_PWR BIT(29)
2976 #define B_AX_RSP_CHK_BASIC_NAV BIT(21)
2977 #define B_AX_RSP_CHK_INTRA_NAV BIT(20)
2978 #define B_AX_RSP_CHK_TXNAV BIT(19)
2979 #define B_AX_TXDATA_END_PS_OPT BIT(18)
2980 #define B_AX_CHECK_SOUNDING_SEQ BIT(17)
2981 #define B_AX_RXBA_IGNOREA2 BIT(16)
2982 #define B_AX_ACKTO_CCK_MASK GENMASK(15, 8)
2983 #define B_AX_ACKTO_MASK GENMASK(7, 0)
2984 
2985 #define R_AX_TRXPTCL_RESP_0 0xCC04
2986 #define R_AX_TRXPTCL_RESP_0_C1 0xEC04
2987 #define B_AX_WMAC_RESP_STBC_EN BIT(31)
2988 #define B_AX_WMAC_RXFTM_TXACK_SC BIT(30)
2989 #define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29)
2990 #define B_AX_RSP_CHK_SEC_CCA_80 BIT(28)
2991 #define B_AX_RSP_CHK_SEC_CCA_40 BIT(27)
2992 #define B_AX_RSP_CHK_SEC_CCA_20 BIT(26)
2993 #define B_AX_RSP_CHK_BTCCA BIT(25)
2994 #define B_AX_RSP_CHK_EDCCA BIT(24)
2995 #define B_AX_RSP_CHK_CCA BIT(23)
2996 #define B_AX_WMAC_LDPC_EN BIT(22)
2997 #define B_AX_WMAC_SGIEN BIT(21)
2998 #define B_AX_WMAC_SPLCPEN BIT(20)
2999 #define B_AX_WMAC_BESP_EARLY_TXBA BIT(17)
3000 #define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
3001 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
3002 #define WMAC_SPEC_SIFS_OFDM_52A 0x15
3003 #define WMAC_SPEC_SIFS_OFDM_52B 0x11
3004 #define WMAC_SPEC_SIFS_OFDM_52C 0x11
3005 #define WMAC_SPEC_SIFS_CCK	 0xA
3006 
3007 #define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08
3008 #define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08
3009 #define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
3010 #define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28)
3011 #define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
3012 #define B_AX_NESS_MASK GENMASK(23, 22)
3013 #define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21)
3014 #define B_AX_WMAC_RESP_DCM_EN BIT(20)
3015 #define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16)
3016 #define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12)
3017 #define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10)
3018 #define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9)
3019 #define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
3020 
3021 #define R_AX_MAC_LOOPBACK 0xCC20
3022 #define R_AX_MAC_LOOPBACK_C1 0xEC20
3023 #define B_AX_MACLBK_EN BIT(0)
3024 
3025 #define R_AX_WMAC_NAV_CTL 0xCC80
3026 #define R_AX_WMAC_NAV_CTL_C1 0xEC80
3027 #define B_AX_WMAC_NAV_UPPER_EN BIT(26)
3028 #define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
3029 #define B_AX_WMAC_PLCP_UP_NAV_EN BIT(17)
3030 #define B_AX_WMAC_TF_UP_NAV_EN BIT(16)
3031 #define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
3032 #define NAV_12MS 0xBC
3033 #define NAV_25MS 0xC4
3034 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
3035 
3036 #define R_AX_RXTRIG_TEST_USER_2 0xCCB0
3037 #define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0
3038 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
3039 #define B_AX_RXTRIG_RU26_DIS BIT(21)
3040 #define B_AX_RXTRIG_FCSCHK_EN BIT(20)
3041 #define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
3042 #define B_AX_RXTRIG_EN BIT(16)
3043 #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
3044 
3045 #define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC
3046 #define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC
3047 #define B_AX_WMAC_MODE BIT(22)
3048 #define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
3049 #define B_AX_RMAC_FTM BIT(8)
3050 #define B_AX_RMAC_CSI BIT(7)
3051 #define B_AX_TMAC_MIMO_CTRL BIT(6)
3052 #define B_AX_TMAC_RXTB BIT(5)
3053 #define B_AX_TMAC_HWSIGB_GEN BIT(4)
3054 #define B_AX_TMAC_TXPLCP BIT(3)
3055 #define B_AX_TMAC_RESP BIT(2)
3056 #define B_AX_TMAC_TXCTL BIT(1)
3057 #define B_AX_TMAC_MACTX BIT(0)
3058 #define B_AX_TMAC_IMR_CLR_V1 (B_AX_TMAC_MACTX | \
3059 			      B_AX_TMAC_TXCTL | \
3060 			      B_AX_TMAC_RESP | \
3061 			      B_AX_TMAC_TXPLCP | \
3062 			      B_AX_TMAC_HWSIGB_GEN | \
3063 			      B_AX_TMAC_RXTB | \
3064 			      B_AX_TMAC_MIMO_CTRL | \
3065 			      B_AX_RMAC_CSI | \
3066 			      B_AX_RMAC_FTM)
3067 #define B_AX_TMAC_IMR_SET_V1 (B_AX_TMAC_MACTX | \
3068 			      B_AX_TMAC_TXCTL | \
3069 			      B_AX_TMAC_RESP | \
3070 			      B_AX_TMAC_TXPLCP | \
3071 			      B_AX_TMAC_HWSIGB_GEN | \
3072 			      B_AX_TMAC_RXTB | \
3073 			      B_AX_TMAC_MIMO_CTRL | \
3074 			      B_AX_RMAC_FTM)
3075 
3076 #define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0
3077 #define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0
3078 #define B_AX_FTM_ERROR_FLAG_CLR BIT(8)
3079 #define B_AX_CSI_ERROR_FLAG_CLR BIT(7)
3080 #define B_AX_MIMOCTRL_ERROR_FLAG_CLR BIT(6)
3081 #define B_AX_RXTB_ERROR_FLAG_CLR BIT(5)
3082 #define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
3083 #define B_AX_TXPLCP_ERROR_FLAG_CLR BIT(3)
3084 #define B_AX_RESP_ERROR_FLAG_CLR BIT(2)
3085 #define B_AX_TXCTL_ERROR_FLAG_CLR BIT(1)
3086 #define B_AX_MACTX_ERROR_FLAG_CLR BIT(0)
3087 
3088 #define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
3089 #define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
3090 #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
3091 
3092 #define R_AX_WMAC_TX_TF_INFO_1 0xCCD4
3093 #define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4
3094 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3095 
3096 #define R_AX_WMAC_TX_TF_INFO_2 0xCCD8
3097 #define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8
3098 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3099 
3100 #define R_AX_TMAC_ERR_IMR_ISR 0xCCEC
3101 #define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC
3102 #define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19)
3103 #define B_AX_TMAC_RESP_ERR_CLR BIT(18)
3104 #define B_AX_TMAC_TXCTL_ERR_CLR BIT(17)
3105 #define B_AX_TMAC_MACTX_ERR_CLR BIT(16)
3106 #define B_AX_TMAC_TXPLCP_ERR BIT(14)
3107 #define B_AX_TMAC_RESP_ERR BIT(13)
3108 #define B_AX_TMAC_TXCTL_ERR BIT(12)
3109 #define B_AX_TMAC_MACTX_ERR BIT(11)
3110 #define B_AX_TMAC_TXPLCP_INT_EN BIT(10)
3111 #define B_AX_TMAC_RESP_INT_EN BIT(9)
3112 #define B_AX_TMAC_TXCTL_INT_EN BIT(8)
3113 #define B_AX_TMAC_MACTX_INT_EN BIT(7)
3114 #define B_AX_WMAC_INT_MODE BIT(6)
3115 #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
3116 #define B_AX_TMAC_IMR_CLR (B_AX_TMAC_MACTX_INT_EN | \
3117 			   B_AX_TMAC_TXCTL_INT_EN | \
3118 			   B_AX_TMAC_RESP_INT_EN | \
3119 			   B_AX_TMAC_TXPLCP_INT_EN)
3120 #define B_AX_TMAC_IMR_SET (B_AX_TMAC_MACTX_INT_EN | \
3121 			   B_AX_TMAC_TXCTL_INT_EN | \
3122 			   B_AX_TMAC_RESP_INT_EN | \
3123 			   B_AX_TMAC_TXPLCP_INT_EN)
3124 
3125 #define R_AX_DBGSEL_TRXPTCL 0xCCF4
3126 #define R_AX_DBGSEL_TRXPTCL_C1 0xECF4
3127 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
3128 
3129 #define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8
3130 #define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8
3131 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16)
3132 #define B_AX_CSI_ON_TIMEOUT_EN BIT(5)
3133 #define B_AX_STS_ON_TIMEOUT_EN BIT(4)
3134 #define B_AX_DATA_ON_TIMEOUT_EN BIT(3)
3135 #define B_AX_OFDM_CCA_TIMEOUT_EN BIT(2)
3136 #define B_AX_CCK_CCA_TIMEOUT_EN BIT(1)
3137 #define B_AX_PHY_TXON_TIMEOUT_EN BIT(0)
3138 #define B_AX_PHYINFO_IMR_CLR_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \
3139 				 B_AX_CCK_CCA_TIMEOUT_EN | \
3140 				 B_AX_OFDM_CCA_TIMEOUT_EN | \
3141 				 B_AX_DATA_ON_TIMEOUT_EN | \
3142 				 B_AX_STS_ON_TIMEOUT_EN | \
3143 				 B_AX_CSI_ON_TIMEOUT_EN)
3144 #define B_AX_PHYINFO_IMR_SET_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \
3145 				 B_AX_CCK_CCA_TIMEOUT_EN | \
3146 				 B_AX_OFDM_CCA_TIMEOUT_EN | \
3147 				 B_AX_DATA_ON_TIMEOUT_EN | \
3148 				 B_AX_STS_ON_TIMEOUT_EN | \
3149 				 B_AX_CSI_ON_TIMEOUT_EN)
3150 
3151 #define R_AX_PHYINFO_ERR_IMR 0xCCFC
3152 #define R_AX_PHYINFO_ERR_IMR_C1 0xECFC
3153 #define B_AX_CSI_ON_TIMEOUT BIT(29)
3154 #define B_AX_STS_ON_TIMEOUT BIT(28)
3155 #define B_AX_DATA_ON_TIMEOUT BIT(27)
3156 #define B_AX_OFDM_CCA_TIMEOUT BIT(26)
3157 #define B_AX_CCK_CCA_TIMEOUT BIT(25)
3158 #define B_AXC_PHY_TXON_TIMEOUT BIT(24)
3159 #define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21)
3160 #define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20)
3161 #define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19)
3162 #define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18)
3163 #define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17)
3164 #define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16)
3165 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
3166 #define B_AX_PHYINFO_IMR_EN_ALL (B_AX_PHY_TXON_TIMEOUT_INT_EN | \
3167 				 B_AX_CCK_CCA_TIMEOUT_INT_EN | \
3168 				 B_AX_OFDM_CCA_TIMEOUT_INT_EN | \
3169 				 B_AX_DATA_ON_TIMEOUT_INT_EN | \
3170 				 B_AX_STS_ON_TIMEOUT_INT_EN | \
3171 				 B_AX_CSI_ON_TIMEOUT_INT_EN | \
3172 				 B_AX_PHYINTF_TIMEOUT_THR_MSAK)
3173 #define B_AX_PHYINFO_IMR_SET (B_AX_PHY_TXON_TIMEOUT_INT_EN | 0x7)
3174 
3175 #define R_AX_PHYINFO_ERR_ISR 0xCCFC
3176 #define R_AX_PHYINFO_ERR_ISR_C1 0xECFC
3177 
3178 #define R_AX_BFMER_CTRL_0 0xCD78
3179 #define R_AX_BFMER_CTRL_0_C1 0xED78
3180 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
3181 #define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16)
3182 #define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8)
3183 #define B_AX_BFMER_NDP_BFEN BIT(2)
3184 #define B_AX_BFMER_VHT_BFPRT_CHK BIT(0)
3185 
3186 #define R_AX_BFMEE_RESP_OPTION 0xCD80
3187 #define R_AX_BFMEE_RESP_OPTION_C1 0xED80
3188 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
3189 #define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)
3190 #define BFRP_RX_STANDBY_TIMER_KEEP 0x0
3191 #define BFRP_RX_STANDBY_TIMER_RELEASE 0x1
3192 #define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)
3193 #define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16)
3194 #define BFRP_RX_STANDBY_TIMER		0x0
3195 #define NDP_RX_STANDBY_TIMER		0xFF
3196 #define B_AX_BFMEE_HE_NDPA_EN BIT(2)
3197 #define B_AX_BFMEE_VHT_NDPA_EN BIT(1)
3198 #define B_AX_BFMEE_HT_NDPA_EN BIT(0)
3199 
3200 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88
3201 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88
3202 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94
3203 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94
3204 #define B_AX_BFMEE_CSISEQ_SEL BIT(29)
3205 #define B_AX_BFMEE_BFPARAM_SEL BIT(28)
3206 #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
3207 #define B_AX_BFMEE_BF_PORT_SEL BIT(23)
3208 #define B_AX_BFMEE_USE_NSTS BIT(22)
3209 #define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21)
3210 #define B_AX_BFMEE_CSI_GID_SEL BIT(20)
3211 #define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
3212 #define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17)
3213 #define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16)
3214 #define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15)
3215 #define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14)
3216 #define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13)
3217 #define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12)
3218 #define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
3219 #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
3220 #define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
3221 #define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
3222 #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
3223 
3224 #define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C
3225 #define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C
3226 #define CSI_RRSC_BMAP 0x29292911
3227 
3228 #define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90
3229 #define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90
3230 #define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16)
3231 #define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8)
3232 #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
3233 #define CSI_INIT_RATE_HE		0x3
3234 #define CSI_INIT_RATE_VHT		0x3
3235 #define CSI_INIT_RATE_HT		0x3
3236 
3237 #define R_AX_RCR 0xCE00
3238 #define R_AX_RCR_C1 0xEE00
3239 #define B_AX_STOP_RX_IN BIT(11)
3240 #define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8)
3241 #define B_AX_CH_EN_MASK GENMASK(3, 0)
3242 
3243 #define R_AX_DLK_PROTECT_CTL 0xCE02
3244 #define R_AX_DLK_PROTECT_CTL_C1 0xEE02
3245 #define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
3246 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
3247 #define B_AX_RX_DLK_RST_EN BIT(1)
3248 #define B_AX_RX_DLK_INT_EN BIT(0)
3249 
3250 #define R_AX_PLCP_HDR_FLTR 0xCE04
3251 #define R_AX_PLCP_HDR_FLTR_C1 0xEE04
3252 #define B_AX_DIS_CHK_MIN_LEN BIT(8)
3253 #define B_AX_HE_SIGB_CRC_CHK BIT(6)
3254 #define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5)
3255 #define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4)
3256 #define B_AX_SIGA_CRC_CHK BIT(3)
3257 #define B_AX_LSIG_PARITY_CHK_EN BIT(2)
3258 #define B_AX_CCK_SIG_CHK BIT(1)
3259 #define B_AX_CCK_CRC_CHK BIT(0)
3260 
3261 #define R_AX_RX_FLTR_OPT 0xCE20
3262 #define R_AX_RX_FLTR_OPT_C1 0xEE20
3263 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
3264 #define B_AX_UNSPT_FILTER_SH 22
3265 #define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22)
3266 #define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
3267 #define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f
3268 #define B_AX_A_FTM_REQ BIT(14)
3269 #define B_AX_A_ERR_PKT BIT(13)
3270 #define B_AX_A_UNSUP_PKT BIT(12)
3271 #define B_AX_A_CRC32_ERR BIT(11)
3272 #define B_AX_A_PWR_MGNT BIT(10)
3273 #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
3274 #define B_AX_A_BCN_CHK_EN BIT(7)
3275 #define B_AX_A_MC_LIST_CAM_MATCH BIT(6)
3276 #define B_AX_A_BC_CAM_MATCH BIT(5)
3277 #define B_AX_A_UC_CAM_MATCH BIT(4)
3278 #define B_AX_A_MC BIT(3)
3279 #define B_AX_A_BC BIT(2)
3280 #define B_AX_A_A1_MATCH BIT(1)
3281 #define B_AX_SNIFFER_MODE BIT(0)
3282 #define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC |	       \
3283 			    B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH |	       \
3284 			    B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ |		       \
3285 			    u32_encode_bits(3, B_AX_UID_FILTER_MASK) |	       \
3286 			    B_AX_A_BCN_CHK_EN)
3287 #define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK)
3288 
3289 #define R_AX_CTRL_FLTR 0xCE24
3290 #define R_AX_CTRL_FLTR_C1 0xEE24
3291 #define R_AX_MGNT_FLTR 0xCE28
3292 #define R_AX_MGNT_FLTR_C1 0xEE28
3293 #define R_AX_DATA_FLTR 0xCE2C
3294 #define R_AX_DATA_FLTR_C1 0xEE2C
3295 #define RX_FLTR_FRAME_DROP	0x00000000
3296 #define RX_FLTR_FRAME_TO_HOST	0x55555555
3297 #define RX_FLTR_FRAME_TO_WLCPU	0xAAAAAAAA
3298 
3299 #define R_AX_ADDR_CAM_CTRL 0xCE34
3300 #define R_AX_ADDR_CAM_CTRL_C1 0xEE34
3301 #define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
3302 #define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
3303 #define B_AX_ADDR_CAM_CLR BIT(8)
3304 #define B_AX_ADDR_CAM_A2_B0_CHK BIT(2)
3305 #define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1)
3306 #define B_AX_ADDR_CAM_EN BIT(0)
3307 
3308 #define R_AX_RESPBA_CAM_CTRL 0xCE3C
3309 #define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C
3310 #define B_AX_SSN_SEL BIT(2)
3311 #define B_AX_BACAM_RST_MASK GENMASK(1, 0)
3312 #define S_AX_BACAM_RST_ALL 2
3313 
3314 #define R_AX_PPDU_STAT 0xCE40
3315 #define R_AX_PPDU_STAT_C1 0xEE40
3316 #define B_AX_PPDU_STAT_RPT_TRIG BIT(8)
3317 #define B_AX_PPDU_STAT_RPT_CRC32 BIT(5)
3318 #define B_AX_PPDU_STAT_RPT_A1M BIT(4)
3319 #define B_AX_APP_PLCP_HDR_RPT BIT(3)
3320 #define B_AX_APP_RX_CNT_RPT BIT(2)
3321 #define B_AX_APP_MAC_INFO_RPT BIT(1)
3322 #define B_AX_PPDU_STAT_RPT_EN BIT(0)
3323 
3324 #define R_AX_RX_SR_CTRL 0xCE4A
3325 #define R_AX_RX_SR_CTRL_C1 0xEE4A
3326 #define B_AX_SR_EN BIT(0)
3327 
3328 #define R_AX_BSSID_SRC_CTRL 0xCE4B
3329 #define R_AX_BSSID_SRC_CTRL_C1 0xEE4B
3330 #define B_AX_BSSID_MATCH BIT(3)
3331 #define B_AX_PARTIAL_AID_MATCH BIT(2)
3332 #define B_AX_BSSCOLOR_MATCH BIT(1)
3333 #define B_AX_PLCP_SRC_EN BIT(0)
3334 
3335 #define R_AX_CSIRPT_OPTION 0xCE64
3336 #define R_AX_CSIRPT_OPTION_C1 0xEE64
3337 #define B_AX_CSIPRT_HESU_AID_EN BIT(25)
3338 #define B_AX_CSIPRT_VHTSU_AID_EN BIT(24)
3339 
3340 #define R_AX_RX_STATE_MONITOR 0xCEF0
3341 #define R_AX_RX_STATE_MONITOR_C1 0xEEF0
3342 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3343 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
3344 #define B_AX_STATE_NXT_MASK GENMASK(13, 8)
3345 #define B_AX_STATE_UPD BIT(7)
3346 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
3347 
3348 #define R_AX_RMAC_ERR_ISR 0xCEF4
3349 #define R_AX_RMAC_ERR_ISR_C1 0xEEF4
3350 #define B_AX_RXERR_INTPS_EN BIT(31)
3351 #define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19)
3352 #define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18)
3353 #define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17)
3354 #define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16)
3355 #define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15)
3356 #define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14)
3357 #define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13)
3358 #define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12)
3359 #define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7)
3360 #define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6)
3361 #define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5)
3362 #define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4)
3363 #define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3)
3364 #define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2)
3365 #define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1)
3366 #define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0)
3367 #define B_AX_RMAC_IMR_CLR (B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | \
3368 			   B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | \
3369 			   B_AX_RMAC_DMA_TIMEOUT_INT_EN | \
3370 			   B_AX_RMAC_CCA_TIMEOUT_INT_EN | \
3371 			   B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN | \
3372 			   B_AX_RMAC_CSI_TIMEOUT_INT_EN | \
3373 			   B_AX_RMAC_RX_TIMEOUT_INT_EN | \
3374 			   B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN)
3375 #define B_AX_RMAC_IMR_SET (B_AX_RMAC_DMA_TIMEOUT_INT_EN | \
3376 			   B_AX_RMAC_CSI_TIMEOUT_INT_EN | \
3377 			   B_AX_RMAC_RX_TIMEOUT_INT_EN | \
3378 			   B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN)
3379 
3380 #define R_AX_RX_ERR_IMR 0xCEF8
3381 #define R_AX_RX_ERR_IMR_C1 0xEEF8
3382 #define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
3383 #define B_AX_RX_ERR_STS_ACT_TO_MSK BIT(8)
3384 #define B_AX_RX_ERR_CSI_ACT_TO_MSK BIT(7)
3385 #define B_AX_RX_ERR_ACT_TO_MSK BIT(6)
3386 #define B_AX_CSI_DATAON_ASSERT_TO_MSK BIT(5)
3387 #define B_AX_DATAON_ASSERT_TO_MSK BIT(4)
3388 #define B_AX_CCA_ASSERT_TO_MSK BIT(3)
3389 #define B_AX_RX_ERR_DMA_TO_MSK BIT(2)
3390 #define B_AX_RX_ERR_DATA_TO_MSK BIT(1)
3391 #define B_AX_RX_ERR_CCA_TO_MSK BIT(0)
3392 #define B_AX_RMAC_IMR_CLR_V1 (B_AX_RX_ERR_CCA_TO_MSK | \
3393 			      B_AX_RX_ERR_DATA_TO_MSK | \
3394 			      B_AX_RX_ERR_DMA_TO_MSK | \
3395 			      B_AX_CCA_ASSERT_TO_MSK | \
3396 			      B_AX_DATAON_ASSERT_TO_MSK | \
3397 			      B_AX_CSI_DATAON_ASSERT_TO_MSK | \
3398 			      B_AX_RX_ERR_ACT_TO_MSK | \
3399 			      B_AX_RX_ERR_CSI_ACT_TO_MSK | \
3400 			      B_AX_RX_ERR_STS_ACT_TO_MSK | \
3401 			      B_AX_RX_ERR_TRIG_ACT_TO_MSK)
3402 #define B_AX_RMAC_IMR_SET_V1 (B_AX_RX_ERR_CCA_TO_MSK | \
3403 			      B_AX_RX_ERR_DATA_TO_MSK | \
3404 			      B_AX_RX_ERR_DMA_TO_MSK | \
3405 			      B_AX_CCA_ASSERT_TO_MSK | \
3406 			      B_AX_DATAON_ASSERT_TO_MSK | \
3407 			      B_AX_CSI_DATAON_ASSERT_TO_MSK | \
3408 			      B_AX_RX_ERR_ACT_TO_MSK | \
3409 			      B_AX_RX_ERR_CSI_ACT_TO_MSK | \
3410 			      B_AX_RX_ERR_STS_ACT_TO_MSK | \
3411 			      B_AX_RX_ERR_TRIG_ACT_TO_MSK)
3412 
3413 #define R_AX_RMAC_PLCP_MON 0xCEF8
3414 #define R_AX_RMAC_PLCP_MON_C1 0xEEF8
3415 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3416 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
3417 #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
3418 
3419 #define R_AX_RX_DEBUG_SELECT 0xCEFC
3420 #define R_AX_RX_DEBUG_SELECT_C1 0xEEFC
3421 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
3422 
3423 #define R_AX_PWR_RATE_CTRL 0xD200
3424 #define R_AX_PWR_RATE_CTRL_C1 0xF200
3425 #define B_AX_PWR_REF GENMASK(27, 10)
3426 #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
3427 #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
3428 
3429 #define R_AX_PWR_RATE_OFST_CTRL 0xD204
3430 #define R_AX_PWR_COEXT_CTRL 0xD220
3431 #define B_AX_TXAGC_BT_EN BIT(1)
3432 #define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
3433 
3434 #define R_AX_PWR_SWING_OTHER_CTRL0 0xD230
3435 #define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230
3436 #define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0)
3437 
3438 #define R_AX_PWR_UL_CTRL0 0xD240
3439 #define R_AX_PWR_UL_CTRL2 0xD248
3440 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
3441 #define B_AX_PWR_UL_CTRL2_MASK 0x07700007
3442 
3443 #define R_AX_PWR_NORM_FORCE1 0xD260
3444 #define R_AX_PWR_NORM_FORCE1_C1 0xF260
3445 #define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29)
3446 #define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24)
3447 #define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23)
3448 #define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22)
3449 #define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21)
3450 #define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20)
3451 #define B_AX_FORCE_BT_GRANT_EN BIT(19)
3452 #define B_AX_FORCE_BT_GRANT_VALUE BIT(18)
3453 #define B_AX_FORCE_RX_LTE_EN BIT(17)
3454 #define B_AX_FORCE_RX_LTE_VALUE BIT(16)
3455 #define B_AX_FORCE_TXBF_EN_EN BIT(15)
3456 #define B_AX_FORCE_TXBF_EN_VALUE BIT(14)
3457 #define B_AX_FORCE_TXSC_EN BIT(13)
3458 #define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9)
3459 #define B_AX_FORCE_NTX_EN BIT(6)
3460 #define B_AX_FORCE_NTX_VALUE BIT(5)
3461 #define B_AX_FORCE_PWR_MODE_EN BIT(3)
3462 #define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)
3463 
3464 #define R_AX_PWR_UL_TB_CTRL 0xD288
3465 #define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
3466 #define R_AX_PWR_UL_TB_1T 0xD28C
3467 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3468 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
3469 #define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24)
3470 #define R_AX_PWR_UL_TB_2T 0xD290
3471 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3472 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3473 #define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24)
3474 #define R_AX_PWR_BY_RATE_TABLE0 0xD2C0
3475 #define R_AX_PWR_BY_RATE_TABLE6 0xD2D8
3476 #define R_AX_PWR_BY_RATE_TABLE10 0xD2E8
3477 #define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0
3478 #define R_AX_PWR_BY_RATE_1SS_MAX R_AX_PWR_BY_RATE_TABLE6
3479 #define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10
3480 #define R_AX_PWR_LMT_TABLE0 0xD2EC
3481 #define R_AX_PWR_LMT_TABLE9 0xD310
3482 #define R_AX_PWR_LMT_TABLE19 0xD338
3483 #define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0
3484 #define R_AX_PWR_LMT_1SS_MAX R_AX_PWR_LMT_TABLE9
3485 #define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19
3486 #define R_AX_PWR_RU_LMT_TABLE0 0xD33C
3487 #define R_AX_PWR_RU_LMT_TABLE5 0xD350
3488 #define R_AX_PWR_RU_LMT_TABLE11 0xD368
3489 #define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0
3490 #define R_AX_PWR_RU_LMT_1SS_MAX R_AX_PWR_RU_LMT_TABLE5
3491 #define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11
3492 #define R_AX_PWR_MACID_LMT_TABLE0 0xD36C
3493 #define R_AX_PWR_MACID_LMT_TABLE127 0xD568
3494 
3495 #define R_AX_PATH_COM0 0xD800
3496 #define AX_PATH_COM0_DFVAL 0x00000000
3497 #define AX_PATH_COM0_PATHA 0x08889880
3498 #define AX_PATH_COM0_PATHB 0x11111900
3499 #define AX_PATH_COM0_PATHAB 0x19999980
3500 #define R_AX_PATH_COM1 0xD804
3501 #define B_AX_PATH_COM1_NORM_1STS GENMASK(31, 28)
3502 #define AX_PATH_COM1_DFVAL 0x00000000
3503 #define AX_PATH_COM1_PATHA 0x13111111
3504 #define AX_PATH_COM1_PATHB 0x23222222
3505 #define AX_PATH_COM1_PATHAB 0x33333333
3506 #define R_AX_PATH_COM2 0xD808
3507 #define B_AX_PATH_COM2_RESP_1STS_PATH GENMASK(7, 4)
3508 #define AX_PATH_COM2_DFVAL 0x00000000
3509 #define AX_PATH_COM2_PATHA 0x01209313
3510 #define AX_PATH_COM2_PATHB 0x01209323
3511 #define AX_PATH_COM2_PATHAB 0x01209333
3512 #define R_AX_PATH_COM3 0xD80C
3513 #define AX_PATH_COM3_DFVAL 0x49249249
3514 #define R_AX_PATH_COM4 0xD810
3515 #define AX_PATH_COM4_DFVAL 0x1C9C9C49
3516 #define R_AX_PATH_COM5 0xD814
3517 #define AX_PATH_COM5_DFVAL 0x39393939
3518 #define R_AX_PATH_COM6 0xD818
3519 #define AX_PATH_COM6_DFVAL 0x39393939
3520 #define R_AX_PATH_COM7 0xD81C
3521 #define AX_PATH_COM7_DFVAL 0x39393939
3522 #define AX_PATH_COM7_PATHA 0x39393939
3523 #define AX_PATH_COM7_PATHB 0x39383939
3524 #define AX_PATH_COM7_PATHAB 0x39393939
3525 #define R_AX_PATH_COM8 0xD820
3526 #define AX_PATH_COM8_DFVAL 0x00000000
3527 #define AX_PATH_COM8_PATHA 0x00003939
3528 #define AX_PATH_COM8_PATHB 0x00003938
3529 #define AX_PATH_COM8_PATHAB 0x00003939
3530 #define R_AX_PATH_COM9 0xD824
3531 #define AX_PATH_COM9_DFVAL 0x000007C0
3532 #define R_AX_PATH_COM10 0xD828
3533 #define AX_PATH_COM10_DFVAL 0xE0000000
3534 #define R_AX_PATH_COM11 0xD82C
3535 #define AX_PATH_COM11_DFVAL 0x00000000
3536 #define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848
3537 #define B_P80_AT_HIGH_FREQ_BB_WRP BIT(28)
3538 #define R_AX_TSSI_CTRL_HEAD 0xD908
3539 #define R_AX_BANDEDGE_CFG 0xD94C
3540 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3541 #define R_AX_TSSI_CTRL_TAIL 0xD95C
3542 
3543 #define R_AX_TXPWR_IMR 0xD9E0
3544 #define R_AX_TXPWR_IMR_C1 0xF9E0
3545 #define R_AX_TXPWR_ISR 0xD9E4
3546 #define R_AX_TXPWR_ISR_C1 0xF9E4
3547 
3548 #define R_AX_BTC_CFG 0xDA00
3549 #define B_AX_BTC_EN BIT(31)
3550 #define B_AX_EN_EXT_BT_PINMUX BIT(29)
3551 #define B_AX_BTC_RST BIT(28)
3552 #define B_AX_BTC_DBG_SRC_SEL BIT(27)
3553 #define B_AX_BTC_MODE_MASK GENMASK(25, 24)
3554 #define B_AX_INV_WL_ACT2 BIT(17)
3555 #define B_AX_BTG_LNA1_GAIN_SEL BIT(16)
3556 #define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)
3557 #define B_AX_IGN_GNT_BT2_RX BIT(7)
3558 #define B_AX_IGN_GNT_BT2_TX BIT(6)
3559 #define B_AX_IGN_GNT_BT2 BIT(5)
3560 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3561 #define B_AX_DIS_BTC_CLK_G BIT(2)
3562 #define B_AX_GNT_WL_RX_CTRL BIT(1)
3563 #define B_AX_WL_SRC BIT(0)
3564 
3565 #define R_AX_RTK_MODE_CFG_V1 0xDA04
3566 #define R_AX_RTK_MODE_CFG_V1_C1 0xFA04
3567 #define B_AX_BT_BLE_EN_V1 BIT(24)
3568 #define B_AX_BT_ULTRA_EN BIT(16)
3569 #define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)
3570 #define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)
3571 #define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)
3572 #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
3573 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3574 
3575 #define R_AX_WL_PRI_MSK 0xDA10
3576 #define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8)
3577 
3578 #define R_AX_BT_CNT_CFG 0xDA10
3579 #define R_AX_BT_CNT_CFG_C1 0xFA10
3580 #define B_AX_BT_CNT_RST_V1 BIT(1)
3581 #define B_AX_BT_CNT_EN BIT(0)
3582 
3583 #define R_BTC_BT_CNT_HIGH 0xDA14
3584 #define R_BTC_BT_CNT_LOW 0xDA18
3585 
3586 #define R_AX_BTC_FUNC_EN 0xDA20
3587 #define R_AX_BTC_FUNC_EN_C1 0xFA20
3588 #define B_AX_PTA_WL_TX_EN BIT(1)
3589 #define B_AX_PTA_EDCCA_EN BIT(0)
3590 
3591 #define R_BTC_COEX_WL_REQ 0xDA24
3592 #define R_BTC_COEX_WL_REQ_BE 0xE324
3593 #define B_BTC_TX_NULL_HI BIT(23)
3594 #define B_BTC_TX_BCN_HI BIT(22)
3595 #define B_BTC_TX_TRI_HI BIT(17)
3596 #define B_BTC_RSP_ACK_HI BIT(10)
3597 #define B_BTC_PRI_MASK_TX_TIME GENMASK(4, 3)
3598 #define B_BTC_PRI_MASK_RX_TIME_V1 GENMASK(2, 1)
3599 
3600 #define R_BTC_BREAK_TABLE 0xDA2C
3601 #define BTC_BREAK_PARAM 0xf0ffffff
3602 
3603 #define R_BTC_BT_COEX_MSK_TABLE 0xDA30
3604 #define B_BTC_PRI_MASK_RXCCK_V1 BIT(28)
3605 #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
3606 
3607 #define R_AX_BT_COEX_CFG_2 0xDA34
3608 #define R_AX_BT_COEX_CFG_2_C1 0xFA34
3609 #define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12)
3610 #define B_AX_GNT_BT_POLARITY BIT(8)
3611 #define B_AX_TIMER_MASK GENMASK(7, 0)
3612 #define MAC_AX_CSR_RATE 80
3613 
3614 #define R_AX_CSR_MODE 0xDA40
3615 #define R_AX_CSR_MODE_C1 0xFA40
3616 #define B_AX_BT_CNT_RST BIT(16)
3617 #define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12)
3618 #define MAC_AX_CSR_DELAY 0
3619 #define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8)
3620 #define MAC_AX_CSR_TRX_TO 4
3621 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3622 #define MAC_AX_CSR_PRI_TO 5
3623 #define B_AX_WL_ACT_MSK BIT(3)
3624 #define B_AX_STATIS_BT_EN BIT(2)
3625 #define B_AX_WL_ACT_MASK_ENABLE BIT(1)
3626 #define B_AX_ENHANCED_BT BIT(0)
3627 
3628 #define R_AX_BT_BREAK_TABLE 0xDA44
3629 
3630 #define R_AX_BT_STAST_HIGH 0xDA44
3631 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3632 #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
3633 #define R_AX_BT_STAST_LOW 0xDA48
3634 #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
3635 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3636 
3637 #define R_AX_GNT_SW_CTRL 0xDA48
3638 #define R_AX_GNT_SW_CTRL_C1 0xFA48
3639 #define B_AX_WL_ACT2_VAL BIT(21)
3640 #define B_AX_WL_ACT2_SWCTRL BIT(20)
3641 #define B_AX_WL_ACT_VAL BIT(19)
3642 #define B_AX_WL_ACT_SWCTRL BIT(18)
3643 #define B_AX_GNT_BT_RX_VAL BIT(17)
3644 #define B_AX_GNT_BT_RX_SWCTRL BIT(16)
3645 #define B_AX_GNT_BT_TX_VAL BIT(15)
3646 #define B_AX_GNT_BT_TX_SWCTRL BIT(14)
3647 #define B_AX_GNT_WL_RX_VAL BIT(13)
3648 #define B_AX_GNT_WL_RX_SWCTRL BIT(12)
3649 #define B_AX_GNT_WL_TX_VAL BIT(11)
3650 #define B_AX_GNT_WL_TX_SWCTRL BIT(10)
3651 #define B_AX_GNT_BT_RFC_S1_VAL BIT(9)
3652 #define B_AX_GNT_BT_RFC_S1_SWCTRL BIT(8)
3653 #define B_AX_GNT_WL_RFC_S1_VAL BIT(7)
3654 #define B_AX_GNT_WL_RFC_S1_SWCTRL BIT(6)
3655 #define B_AX_GNT_BT_RFC_S0_VAL BIT(5)
3656 #define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4)
3657 #define B_AX_GNT_WL_RFC_S0_VAL BIT(3)
3658 #define B_AX_GNT_WL_RFC_S0_SWCTRL BIT(2)
3659 #define B_AX_GNT_WL_BB_VAL BIT(1)
3660 #define B_AX_GNT_WL_BB_SWCTRL BIT(0)
3661 
3662 #define R_AX_GNT_VAL 0x0054
3663 #define B_AX_GNT_BT_RFC_S1_STA BIT(5)
3664 #define B_AX_GNT_WL_RFC_S1_STA BIT(4)
3665 #define B_AX_GNT_BT_RFC_S0_STA BIT(3)
3666 #define B_AX_GNT_WL_RFC_S0_STA BIT(2)
3667 
3668 #define R_AX_GNT_VAL_V1 0xDA4C
3669 #define B_AX_GNT_BT_RFC_S1 BIT(4)
3670 #define B_AX_GNT_BT_RFC_S0 BIT(3)
3671 #define B_AX_GNT_WL_RFC_S1 BIT(2)
3672 #define B_AX_GNT_WL_RFC_S0 BIT(1)
3673 
3674 #define R_AX_TDMA_MODE 0xDA4C
3675 #define R_AX_TDMA_MODE_C1 0xFA4C
3676 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3677 #define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8)
3678 #define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)
3679 #define B_AX_TDMA_BT_START_NOTIFY BIT(5)
3680 #define B_AX_ENABLE_TDMA_FW_MODE BIT(4)
3681 #define B_AX_ENABLE_PTA_TDMA_MODE BIT(3)
3682 #define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
3683 #define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
3684 #define B_AX_RTK_BT_ENABLE BIT(0)
3685 
3686 #define R_AX_BT_COEX_CFG_5 0xDA6C
3687 #define R_AX_BT_COEX_CFG_5_C1 0xFA6C
3688 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3689 #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
3690 #define MAC_AX_RTK_RATE 5
3691 
3692 #define R_AX_LTE_CTRL 0xDAF0
3693 #define R_AX_LTE_WDATA 0xDAF4
3694 #define R_AX_LTE_RDATA 0xDAF8
3695 
3696 #define R_AX_MACID_ANT_TABLE 0xDC00
3697 #define R_AX_MACID_ANT_TABLE_LAST 0xDDFC
3698 
3699 #define CMAC1_START_ADDR_AX 0xE000
3700 #define CMAC1_END_ADDR_AX 0xFFFF
3701 #define R_AX_CMAC_REG_END 0xFFFF
3702 
3703 #define R_AX_LTE_SW_CFG_1 0x0038
3704 #define R_AX_LTE_SW_CFG_1_C1 0x2038
3705 #define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
3706 #define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30)
3707 #define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29)
3708 #define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28)
3709 #define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27)
3710 #define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26)
3711 #define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25)
3712 #define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24)
3713 #define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19)
3714 #define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18)
3715 #define B_AX_LTE_PATTERN_2_EN BIT(17)
3716 #define B_AX_LTE_PATTERN_1_EN BIT(16)
3717 #define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15)
3718 #define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14)
3719 #define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13)
3720 #define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12)
3721 #define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11)
3722 #define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10)
3723 #define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9)
3724 #define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8)
3725 #define B_AX_LTECOEX_FUN_EN BIT(7)
3726 #define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6)
3727 #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
3728 #define B_AX_LTECOEX_UART_MUX BIT(3)
3729 #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
3730 
3731 #define R_AX_LTE_SW_CFG_2 0x003C
3732 #define R_AX_LTE_SW_CFG_2_C1 0x203C
3733 #define B_AX_WL_RX_CTRL BIT(8)
3734 #define B_AX_GNT_WL_RX_SW_VAL BIT(7)
3735 #define B_AX_GNT_WL_RX_SW_CTRL BIT(6)
3736 #define B_AX_GNT_WL_TX_SW_VAL BIT(5)
3737 #define B_AX_GNT_WL_TX_SW_CTRL BIT(4)
3738 #define B_AX_GNT_BT_RX_SW_VAL BIT(3)
3739 #define B_AX_GNT_BT_RX_SW_CTRL BIT(2)
3740 #define B_AX_GNT_BT_TX_SW_VAL BIT(1)
3741 #define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
3742 
3743 #define R_BE_SYS_ISO_CTRL 0x0000
3744 #define B_BE_PWC_EV2EF_B BIT(15)
3745 #define B_BE_PWC_EV2EF_S BIT(14)
3746 #define B_BE_PA33V_EN BIT(13)
3747 #define B_BE_PA12V_EN BIT(12)
3748 #define B_BE_PAOOBS33V_EN BIT(11)
3749 #define B_BE_PAOOBS12V_EN BIT(10)
3750 #define B_BE_ISO_RFDIO BIT(9)
3751 #define B_BE_ISO_EB2CORE BIT(8)
3752 #define B_BE_ISO_DIOE BIT(7)
3753 #define B_BE_ISO_WLPON2PP BIT(6)
3754 #define B_BE_ISO_IP2MAC_WA02PP BIT(5)
3755 #define B_BE_ISO_PD2CORE BIT(4)
3756 #define B_BE_ISO_PA2PCIE BIT(3)
3757 #define B_BE_ISO_PAOOBS2PCIE BIT(1)
3758 #define B_BE_ISO_WD2PP BIT(0)
3759 
3760 #define R_BE_SYS_PW_CTRL 0x0004
3761 #define B_BE_SOP_ASWRM BIT(31)
3762 #define B_BE_SOP_EASWR BIT(30)
3763 #define B_BE_SOP_PWMM_DSWR BIT(29)
3764 #define B_BE_SOP_EDSWR BIT(28)
3765 #define B_BE_SOP_ACKF BIT(27)
3766 #define B_BE_SOP_ERCK BIT(26)
3767 #define B_BE_SOP_ANA_CLK_DIVISION_2 BIT(25)
3768 #define B_BE_SOP_EXTL BIT(24)
3769 #define B_BE_SOP_OFF_CAPC_EN BIT(23)
3770 #define B_BE_XTAL_OFF_A_DIE BIT(22)
3771 #define B_BE_ROP_SWPR BIT(21)
3772 #define B_BE_DIS_HW_LPLDM BIT(20)
3773 #define B_BE_DIS_HW_LPURLDO BIT(19)
3774 #define B_BE_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
3775 #define B_BE_RDY_SYSPWR BIT(17)
3776 #define B_BE_EN_WLON BIT(16)
3777 #define B_BE_APDM_HPDN BIT(15)
3778 #define B_BE_PSUS_OFF_CAPC_EN BIT(14)
3779 #define B_BE_AFSM_PCIE_SUS_EN BIT(12)
3780 #define B_BE_AFSM_WLSUS_EN BIT(11)
3781 #define B_BE_APFM_SWLPS BIT(10)
3782 #define B_BE_APFM_OFFMAC BIT(9)
3783 #define B_BE_APFN_ONMAC BIT(8)
3784 #define B_BE_CHIP_PDN_EN BIT(7)
3785 #define B_BE_RDY_MACDIS BIT(6)
3786 
3787 #define R_BE_SYS_CLK_CTRL 0x0008
3788 #define B_BE_CPU_CLK_EN BIT(14)
3789 #define B_BE_SYMR_BE_CLK_EN BIT(13)
3790 #define B_BE_MAC_CLK_EN BIT(11)
3791 #define B_BE_EXT_32K_EN BIT(8)
3792 #define B_BE_WL_CLK_TEST BIT(7)
3793 #define B_BE_LOADER_CLK_EN BIT(5)
3794 #define B_BE_ANA_CLK_DIVISION_2 BIT(1)
3795 #define B_BE_CNTD16V_EN BIT(0)
3796 
3797 #define R_BE_SYS_WL_EFUSE_CTRL 0x000A
3798 #define B_BE_OTP_B_PWC_RPT BIT(15)
3799 #define B_BE_OTP_S_PWC_RPT BIT(14)
3800 #define B_BE_OTP_ISO_RPT BIT(13)
3801 #define B_BE_OTP_BURST_RPT BIT(12)
3802 #define B_BE_OTP_AUTOLOAD_RPT BIT(11)
3803 #define B_BE_AUTOLOAD_DIS_A_DIE BIT(6)
3804 #define B_BE_AUTOLOAD_SUS BIT(5)
3805 #define B_BE_AUTOLOAD_DIS BIT(4)
3806 
3807 #define R_BE_SYS_PAGE_CLK_GATED 0x000C
3808 #define B_BE_USB_APHY_PC_DLP_OP BIT(27)
3809 #define B_BE_PCIE_APHY_PC_DLP_OP BIT(26)
3810 #define B_BE_UPHY_POWER_READY_CHK BIT(25)
3811 #define B_BE_CPHY_POWER_READY_CHK BIT(24)
3812 #define B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK GENMASK(23, 22)
3813 #define B_BE_SYM_PRST_DEBUNC_SEL BIT(21)
3814 #define B_BE_CPHY_AUXCLK_OP BIT(20)
3815 #define B_BE_SOP_OFFUA_PC BIT(19)
3816 #define B_BE_SOP_OFFPOOBS_PC BIT(18)
3817 #define B_BE_PCIE_LAN1_MASK BIT(17)
3818 #define B_BE_PCIE_LAN0_MASK BIT(16)
3819 #define B_BE_DIS_CLK_REGF_GATE BIT(15)
3820 #define B_BE_DIS_CLK_REGE_GATE BIT(14)
3821 #define B_BE_DIS_CLK_REGD_GATE BIT(13)
3822 #define B_BE_DIS_CLK_REGC_GATE BIT(12)
3823 #define B_BE_DIS_CLK_REGB_GATE BIT(11)
3824 #define B_BE_DIS_CLK_REGA_GATE BIT(10)
3825 #define B_BE_DIS_CLK_REG9_GATE BIT(9)
3826 #define B_BE_DIS_CLK_REG8_GATE BIT(8)
3827 #define B_BE_DIS_CLK_REG7_GATE BIT(7)
3828 #define B_BE_DIS_CLK_REG6_GATE BIT(6)
3829 #define B_BE_DIS_CLK_REG5_GATE BIT(5)
3830 #define B_BE_DIS_CLK_REG4_GATE BIT(4)
3831 #define B_BE_DIS_CLK_REG3_GATE BIT(3)
3832 #define B_BE_DIS_CLK_REG2_GATE BIT(2)
3833 #define B_BE_DIS_CLK_REG1_GATE BIT(1)
3834 #define B_BE_DIS_CLK_REG0_GATE BIT(0)
3835 
3836 #define R_BE_ANAPAR_POW_MAC 0x0016
3837 #define B_BE_POW_PC_LDO_PORT1 BIT(3)
3838 #define B_BE_POW_PC_LDO_PORT0 BIT(2)
3839 #define B_BE_POW_PLL_V1 BIT(1)
3840 #define B_BE_POW_POWER_CUT_POW_LDO BIT(0)
3841 
3842 #define R_BE_SYS_ADIE_PAD_PWR_CTRL 0x0018
3843 #define B_BE_SYM_PADPDN_WL_RFC1_1P3 BIT(6)
3844 #define B_BE_SYM_PADPDN_WL_RFC0_1P3 BIT(5)
3845 
3846 #define R_BE_RSV_CTRL 0x001C
3847 #define B_BE_HR_BE_DBG GENMASK(23, 12)
3848 #define B_BE_R_SYM_DIS_PCIE_FLR BIT(9)
3849 #define B_BE_R_EN_HRST_PWRON BIT(8)
3850 #define B_BE_LOCK_ALL_EN BIT(7)
3851 #define B_BE_R_DIS_PRST BIT(6)
3852 #define B_BE_WLOCK_1C_BIT6 BIT(5)
3853 #define B_BE_WLOCK_40 BIT(4)
3854 #define B_BE_WLOCK_08 BIT(3)
3855 #define B_BE_WLOCK_04 BIT(2)
3856 #define B_BE_WLOCK_00 BIT(1)
3857 #define B_BE_WLOCK_ALL BIT(0)
3858 
3859 #define R_BE_AFE_LDO_CTRL 0x0020
3860 #define B_BE_FORCE_MACBBBT_PWR_ON BIT(31)
3861 #define B_BE_R_SYM_WLPOFF_P4_PC_EN BIT(28)
3862 #define B_BE_R_SYM_WLPOFF_P3_PC_EN BIT(27)
3863 #define B_BE_R_SYM_WLPOFF_P2_PC_EN BIT(26)
3864 #define B_BE_R_SYM_WLPOFF_P1_PC_EN BIT(25)
3865 #define B_BE_R_SYM_WLPOFF_PC_EN BIT(24)
3866 #define B_BE_AON_OFF_PC_EN BIT(23)
3867 #define B_BE_R_SYM_WLPON_P3_PC_EN BIT(21)
3868 #define B_BE_R_SYM_WLPON_P2_PC_EN BIT(20)
3869 #define B_BE_R_SYM_WLPON_P1_PC_EN BIT(19)
3870 #define B_BE_R_SYM_WLPON_PC_EN BIT(18)
3871 #define B_BE_R_SYM_WLBBPON1_P1_PC_EN BIT(15)
3872 #define B_BE_R_SYM_WLBBPON1_PC_EN BIT(14)
3873 #define B_BE_R_SYM_WLBBPON_P1_PC_EN BIT(13)
3874 #define B_BE_R_SYM_WLBBPON_PC_EN BIT(12)
3875 #define B_BE_R_SYM_DIS_WPHYBBOFF_PC BIT(10)
3876 #define B_BE_R_SYM_WLBBOFF1_P4_PC_EN BIT(9)
3877 #define B_BE_R_SYM_WLBBOFF1_P3_PC_EN BIT(8)
3878 #define B_BE_R_SYM_WLBBOFF1_P2_PC_EN BIT(7)
3879 #define B_BE_R_SYM_WLBBOFF1_P1_PC_EN BIT(6)
3880 #define B_BE_R_SYM_WLBBOFF1_PC_EN BIT(5)
3881 #define B_BE_R_SYM_WLBBOFF_P4_PC_EN BIT(4)
3882 #define B_BE_R_SYM_WLBBOFF_P3_PC_EN BIT(3)
3883 #define B_BE_R_SYM_WLBBOFF_P2_PC_EN BIT(2)
3884 #define B_BE_R_SYM_WLBBOFF_P1_PC_EN BIT(1)
3885 #define B_BE_R_SYM_WLBBOFF_PC_EN BIT(0)
3886 
3887 #define R_BE_AFE_CTRL1 0x0024
3888 #define B_BE_R_SYM_WLCMAC0_P4_PC_EN BIT(28)
3889 #define B_BE_R_SYM_WLCMAC0_P3_PC_EN BIT(27)
3890 #define B_BE_R_SYM_WLCMAC0_P2_PC_EN BIT(26)
3891 #define B_BE_R_SYM_WLCMAC0_P1_PC_EN BIT(25)
3892 #define B_BE_R_SYM_WLCMAC0_PC_EN BIT(24)
3893 #define B_BE_DATAMEM_PC3_EN BIT(23)
3894 #define B_BE_DATAMEM_PC2_EN BIT(22)
3895 #define B_BE_DATAMEM_PC1_EN BIT(21)
3896 #define B_BE_DATAMEM_PC_EN BIT(20)
3897 #define B_BE_DMEM7_PC_EN BIT(19)
3898 #define B_BE_DMEM6_PC_EN BIT(18)
3899 #define B_BE_DMEM5_PC_EN BIT(17)
3900 #define B_BE_DMEM4_PC_EN BIT(16)
3901 #define B_BE_DMEM3_PC_EN BIT(15)
3902 #define B_BE_DMEM2_PC_EN BIT(14)
3903 #define B_BE_DMEM1_PC_EN BIT(13)
3904 #define B_BE_IMEM4_PC_EN BIT(12)
3905 #define B_BE_IMEM3_PC_EN BIT(11)
3906 #define B_BE_IMEM2_PC_EN BIT(10)
3907 #define B_BE_IMEM1_PC_EN BIT(9)
3908 #define B_BE_IMEM0_PC_EN BIT(8)
3909 #define B_BE_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
3910 #define B_BE_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
3911 #define B_BE_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
3912 #define B_BE_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
3913 #define B_BE_R_SYM_WLCMAC1_PC_EN BIT(0)
3914 #define B_BE_AFE_CTRL1_SET (B_BE_R_SYM_WLCMAC1_PC_EN | \
3915 			    B_BE_R_SYM_WLCMAC1_P1_PC_EN | \
3916 			    B_BE_R_SYM_WLCMAC1_P2_PC_EN | \
3917 			    B_BE_R_SYM_WLCMAC1_P3_PC_EN | \
3918 			    B_BE_R_SYM_WLCMAC1_P4_PC_EN)
3919 
3920 #define R_BE_EFUSE_CTRL 0x0030
3921 #define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)
3922 #define B_BE_EF_RDY BIT(29)
3923 #define B_BE_EF_COMP_RESULT BIT(28)
3924 #define B_BE_EF_ADDR_MASK GENMASK(15, 0)
3925 
3926 #define R_BE_EFUSE_CTRL_1_V1 0x0034
3927 #define B_BE_EF_DATA_MASK GENMASK(31, 0)
3928 
3929 #define R_BE_GPIO_EXT_CTRL 0x0060
3930 #define B_BE_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
3931 #define B_BE_GPIO_MOD_9 BIT(25)
3932 #define B_BE_GPIO_IO_SEL_15_TO_8_MASK GENMASK(23, 16)
3933 #define B_BE_GPIO_IO_SEL_9 BIT(17)
3934 #define B_BE_GPIO_OUT_15_TO_8_MASK GENMASK(15, 8)
3935 #define B_BE_GPIO_IN_15_TO_8_MASK GENMASK(7, 0)
3936 #define B_BE_GPIO_IN_9 BIT(1)
3937 
3938 #define R_BE_WL_BT_PWR_CTRL 0x0068
3939 #define B_BE_ISO_BD2PP BIT(31)
3940 #define B_BE_LDOV12B_EN BIT(30)
3941 #define B_BE_CKEN_BT BIT(29)
3942 #define B_BE_FEN_BT BIT(28)
3943 #define B_BE_BTCPU_BOOTSEL BIT(27)
3944 #define B_BE_SPI_SPEEDUP BIT(26)
3945 #define B_BE_BT_LDO_MODE BIT(25)
3946 #define B_BE_ISO_BTPON2PP BIT(22)
3947 #define B_BE_BT_FUNC_EN BIT(18)
3948 #define B_BE_BT_HWPDN_SL BIT(17)
3949 #define B_BE_BT_DISN_EN BIT(16)
3950 #define B_BE_SDM_SRC_SEL BIT(12)
3951 #define B_BE_ISO_BA2PP BIT(11)
3952 #define B_BE_BT_AFE_LDO_EN BIT(10)
3953 #define B_BE_BT_AFE_PLL_EN BIT(9)
3954 #define B_BE_WLAN_32K_SEL BIT(6)
3955 #define B_BE_WL_DRV_EXIST_IDX BIT(5)
3956 #define B_BE_DOP_EHPAD BIT(4)
3957 #define B_BE_WL_FUNC_EN BIT(2)
3958 #define B_BE_WL_HWPDN_SL BIT(1)
3959 #define B_BE_WL_HWPDN_EN BIT(0)
3960 
3961 #define R_BE_SYS_SDIO_CTRL 0x0070
3962 #define B_BE_MCM_FLASH_EN BIT(28)
3963 #define B_BE_PCIE_SEC_LOAD BIT(26)
3964 #define B_BE_PCIE_SER_RSTB BIT(25)
3965 #define B_BE_PCIE_SEC_LOAD_CLR BIT(24)
3966 #define B_BE_SDIO_CMD_SW_RST BIT(20)
3967 #define B_BE_SDIO_INT_POLARITY BIT(19)
3968 #define B_BE_SDIO_OFF_EN BIT(17)
3969 #define B_BE_SDIO_ON_EN BIT(16)
3970 #define B_BE_PCIE_DIS_L2__CTRL_LDO_HCI BIT(15)
3971 #define B_BE_PCIE_DIS_L2_RTK_PERST BIT(14)
3972 #define B_BE_PCIE_FORCE_PWR_NGAT BIT(13)
3973 #define B_BE_PCIE_FORCE_IBX_EN BIT(12)
3974 #define B_BE_PCIE_AUXCLK_GATE BIT(11)
3975 #define B_BE_PCIE_WAIT_TIMEOUT_EVENT BIT(10)
3976 #define B_BE_PCIE_WAIT_TIME BIT(9)
3977 #define B_BE_L1OFF_TO_L0_RESUME_EVT BIT(8)
3978 #define B_BE_USBA_FORCE_PWR_NGAT BIT(7)
3979 #define B_BE_USBD_FORCE_PWR_NGAT BIT(6)
3980 #define B_BE_BT_CTRL_USB_PWR BIT(5)
3981 #define B_BE_USB_D_STATE_HOLD BIT(4)
3982 #define B_BE_R_BE_FORCE_DP BIT(3)
3983 #define B_BE_R_BE_DP_MODE BIT(2)
3984 #define B_BE_RES_USB_MASS_STORAGE_DESC BIT(1)
3985 #define B_BE_USB_WAIT_TIME BIT(0)
3986 
3987 #define R_BE_HCI_OPT_CTRL 0x0074
3988 #define B_BE_HCI_WLAN_IO_ST BIT(31)
3989 #define B_BE_HCI_WLAN_IO_EN BIT(28)
3990 #define B_BE_HAXIDMA_IO_ST BIT(27)
3991 #define B_BE_HAXIDMA_BACKUP_RESTORE_ST BIT(26)
3992 #define B_BE_HAXIDMA_IO_EN BIT(24)
3993 #define B_BE_EN_PCIE_WAKE BIT(23)
3994 #define B_BE_SDIO_PAD_H3L1 BIT(22)
3995 #define B_BE_USBMAC_ANACLK_SW BIT(21)
3996 #define B_BE_PCIE_CPHY_CCK_XTAL_SEL BIT(20)
3997 #define B_BE_SDIO_DATA_PAD_SMT BIT(19)
3998 #define B_BE_SDIO_PAD_E5 BIT(18)
3999 #define B_BE_FORCE_PCIE_AUXCLK BIT(17)
4000 #define B_BE_HCI_LA_ADDR_MAP BIT(16)
4001 #define B_BE_HCI_LA_GLO_RST BIT(15)
4002 #define B_BE_USB3_SUS_DIS BIT(14)
4003 #define B_BE_NOPWR_CTRL_SEL BIT(13)
4004 #define B_BE_USB_HOST_PWR_OFF_EN BIT(12)
4005 #define B_BE_SYM_LPS_BLOCK_EN BIT(11)
4006 #define B_BE_USB_LPM_ACT_EN BIT(10)
4007 #define B_BE_USB_LPM_NY BIT(9)
4008 #define B_BE_USB2_SUS_DIS BIT(8)
4009 #define B_BE_SDIO_PAD_E_MASK GENMASK(7, 5)
4010 #define B_BE_USB_LPPLL_EN BIT(4)
4011 #define B_BE_USB1_1_USB2_0_DECISION BIT(3)
4012 #define B_BE_ROP_SW15 BIT(2)
4013 #define B_BE_PCI_CKRDY_OPT BIT(1)
4014 #define B_BE_PCI_VAUX_EN BIT(0)
4015 
4016 #define R_BE_SYS_ISO_CTRL_EXTEND 0x0080
4017 #define B_BE_R_SYM_ISO_DMEM62PP BIT(29)
4018 #define B_BE_R_SYM_ISO_DMEM52PP BIT(28)
4019 #define B_BE_R_SYM_ISO_DMEM42PP BIT(27)
4020 #define B_BE_R_SYM_ISO_DMEM32PP BIT(26)
4021 #define B_BE_R_SYM_ISO_DMEM22PP BIT(25)
4022 #define B_BE_R_SYM_ISO_DMEM12PP BIT(24)
4023 #define B_BE_R_SYM_ISO_IMEM42PP BIT(22)
4024 #define B_BE_R_SYM_ISO_IMEM32PP BIT(21)
4025 #define B_BE_R_SYM_ISO_IMEM22PP BIT(20)
4026 #define B_BE_R_SYM_ISO_IMEM12PP BIT(19)
4027 #define B_BE_R_SYM_ISO_IMEM02PP BIT(18)
4028 #define B_BE_R_SYM_ISO_AON_OFF2PP BIT(15)
4029 #define B_BE_R_SYM_PWC_HCILA BIT(13)
4030 #define B_BE_R_SYM_PWC_PD12V BIT(12)
4031 #define B_BE_R_SYM_PWC_UD12V BIT(11)
4032 #define B_BE_R_SYM_PWC_BTBRG BIT(10)
4033 #define B_BE_R_SYM_LDOBTSDIO_EN BIT(9)
4034 #define B_BE_R_SYM_LDOSPDIO_EN BIT(8)
4035 #define B_BE_R_SYM_ISO_HCILA BIT(4)
4036 #define B_BE_R_SYM_ISO_BTBRG2PP BIT(2)
4037 #define B_BE_R_SYM_ISO_BTSDIO2PP BIT(1)
4038 #define B_BE_R_SYM_ISO_SPDIO2PP BIT(0)
4039 
4040 #define R_BE_FEN_RST_ENABLE 0x0084
4041 #define B_BE_R_SYM_FEN_WLMACOFF BIT(31)
4042 #define B_BE_R_SYM_ISO_WA12PP BIT(28)
4043 #define B_BE_R_SYM_ISO_CMAC12PP BIT(25)
4044 #define B_BE_R_SYM_ISO_CMAC02PP BIT(24)
4045 #define B_BE_R_SYM_ISO_ADDA_P32PP BIT(23)
4046 #define B_BE_R_SYM_ISO_ADDA_P22PP BIT(22)
4047 #define B_BE_R_SYM_ISO_ADDA_P12PP BIT(21)
4048 #define B_BE_R_SYM_ISO_ADDA_P02PP BIT(20)
4049 #define B_BE_CMAC1_FEN BIT(17)
4050 #define B_BE_CMAC0_FEN BIT(16)
4051 #define B_BE_SYM_ISO_BBPON12PP BIT(13)
4052 #define B_BE_SYM_ISO_BB12PP BIT(12)
4053 #define B_BE_BOOT_RDY1 BIT(10)
4054 #define B_BE_FEN_BB1_IP_RSTN BIT(9)
4055 #define B_BE_FEN_BB1PLAT_RSTB BIT(8)
4056 #define B_BE_SYM_ISO_BBPON02PP BIT(5)
4057 #define B_BE_SYM_ISO_BB02PP BIT(4)
4058 #define B_BE_BOOT_RDY0 BIT(2)
4059 #define B_BE_FEN_BB_IP_RSTN BIT(1)
4060 #define B_BE_FEN_BBPLAT_RSTB BIT(0)
4061 
4062 #define R_BE_PLATFORM_ENABLE 0x0088
4063 #define B_BE_HOLD_AFTER_RESET BIT(11)
4064 #define B_BE_SYM_WLPLT_MEM_MUX_EN BIT(10)
4065 #define B_BE_WCPU_WARM_EN BIT(9)
4066 #define B_BE_SPIC_EN BIT(8)
4067 #define B_BE_UART_EN BIT(7)
4068 #define B_BE_IDDMA_EN BIT(6)
4069 #define B_BE_IPSEC_EN BIT(5)
4070 #define B_BE_HIOE_EN BIT(4)
4071 #define B_BE_APB_WRAP_EN BIT(2)
4072 #define B_BE_WCPU_EN BIT(1)
4073 #define B_BE_PLATFORM_EN BIT(0)
4074 
4075 #define R_BE_WLLPS_CTRL 0x0090
4076 #define B_BE_LPSOP_BBMEMDS BIT(30)
4077 #define B_BE_LPSOP_BBOFF BIT(29)
4078 #define B_BE_LPSOP_MACOFF BIT(28)
4079 #define B_BE_LPSOP_OFF_CAPC_EN BIT(27)
4080 #define B_BE_LPSOP_MEM_DS BIT(26)
4081 #define B_BE_LPSOP_XTALM_LPS BIT(23)
4082 #define B_BE_LPSOP_XTAL BIT(22)
4083 #define B_BE_LPSOP_ACLK_DIV_2 BIT(21)
4084 #define B_BE_LPSOP_ACLK_SEL BIT(20)
4085 #define B_BE_LPSOP_ASWRM BIT(17)
4086 #define B_BE_LPSOP_ASWR BIT(16)
4087 #define B_BE_LPSOP_DSWR_ADJ_MASK GENMASK(15, 12)
4088 #define B_BE_LPSOP_DSWRSD BIT(10)
4089 #define B_BE_LPSOP_DSWRM BIT(9)
4090 #define B_BE_LPSOP_DSWR BIT(8)
4091 #define B_BE_LPSOP_OLD_ADJ_MASK GENMASK(7, 4)
4092 #define B_BE_FORCE_LEAVE_LPS BIT(3)
4093 #define B_BE_LPSOP_OLDSD BIT(2)
4094 #define B_BE_DIS_WLBT_LPSEN_LOPC BIT(1)
4095 #define B_BE_WL_LPS_EN BIT(0)
4096 
4097 #define R_BE_WLRESUME_CTRL 0x0094
4098 #define B_BE_LPSROP_DMEM5_RSU_EN BIT(31)
4099 #define B_BE_LPSROP_DMEM4_RSU_EN BIT(30)
4100 #define B_BE_LPSROP_DMEM3_RSU_EN BIT(29)
4101 #define B_BE_LPSROP_DMEM2_RSU_EN BIT(28)
4102 #define B_BE_LPSROP_DMEM1_RSU_EN BIT(27)
4103 #define B_BE_LPSROP_DMEM0_RSU_EN BIT(26)
4104 #define B_BE_LPSROP_IMEM5_RSU_EN BIT(25)
4105 #define B_BE_LPSROP_IMEM4_RSU_EN BIT(24)
4106 #define B_BE_LPSROP_IMEM3_RSU_EN BIT(23)
4107 #define B_BE_LPSROP_IMEM2_RSU_EN BIT(22)
4108 #define B_BE_LPSROP_IMEM1_RSU_EN BIT(21)
4109 #define B_BE_LPSROP_IMEM0_RSU_EN BIT(20)
4110 #define B_BE_LPSROP_BB1_W_BB0 BIT(14)
4111 #define B_BE_LPSROP_CMAC1 BIT(13)
4112 #define B_BE_LPSROP_CMAC0 BIT(12)
4113 #define B_BE_LPSROP_XTALM BIT(11)
4114 #define B_BE_LPSROP_PLLM BIT(10)
4115 #define B_BE_LPSROP_HIOE BIT(9)
4116 #define B_BE_LPSROP_CPU BIT(8)
4117 #define B_BE_LPSROP_LOWPWRPLL BIT(7)
4118 #define B_BE_LPSROP_DSWRSD_SEL_MASK GENMASK(5, 4)
4119 
4120 #define R_BE_EFUSE_CTRL_2_V1 0x00A4
4121 #define B_BE_EF_ENT BIT(31)
4122 #define B_BE_EF_TCOLUMN_EN BIT(29)
4123 #define B_BE_BT_OTP_PWC_DIS BIT(28)
4124 #define B_BE_EF_RDT BIT(27)
4125 #define B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL BIT(24)
4126 #define B_BE_EF_PGTS_MASK GENMASK(23, 20)
4127 #define B_BE_EF_BURST BIT(19)
4128 #define B_BE_EF_TEST_SEL_MASK GENMASK(18, 16)
4129 #define B_BE_EF_TROW_EN BIT(15)
4130 #define B_BE_EF_ERR_FLAG BIT(14)
4131 #define B_BE_EF_FBURST_DIS BIT(13)
4132 #define B_BE_EF_HT_SEL BIT(12)
4133 #define B_BE_EF_DSB_EN BIT(11)
4134 #define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0)
4135 
4136 #define R_BE_PMC_DBG_CTRL2 0x00CC
4137 #define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
4138 #define B_BE_DIS_IOWRAP_TIMEOUT BIT(16)
4139 #define B_BE_STOP_WL_PMC BIT(9)
4140 #define B_BE_STOP_SYM_PMC BIT(8)
4141 #define B_BE_SYM_REG_PCIE_WRMSK BIT(7)
4142 #define B_BE_BT_ACCESS_WL_PAGE0 BIT(6)
4143 #define B_BE_R_BE_RST_WLPMC BIT(5)
4144 #define B_BE_R_BE_RST_PD12N BIT(4)
4145 #define B_BE_SYSON_DIS_WLR_BE_WRMSK BIT(3)
4146 #define B_BE_SYSON_DIS_PMCR_BE_WRMSK BIT(2)
4147 #define B_BE_SYSON_R_BE_ARB_MASK GENMASK(1, 0)
4148 
4149 #define R_BE_MEM_PWR_CTRL 0x00D0
4150 #define B_BE_DMEM5_WLMCU_DS BIT(31)
4151 #define B_BE_DMEM4_WLMCU_DS BIT(30)
4152 #define B_BE_DMEM3_WLMCU_DS BIT(29)
4153 #define B_BE_DMEM2_WLMCU_DS BIT(28)
4154 #define B_BE_DMEM1_WLMCU_DS BIT(27)
4155 #define B_BE_DMEM0_WLMCU_DS BIT(26)
4156 #define B_BE_IMEM5_WLMCU_DS BIT(25)
4157 #define B_BE_IMEM4_WLMCU_DS BIT(24)
4158 #define B_BE_IMEM3_WLMCU_DS BIT(23)
4159 #define B_BE_IMEM2_WLMCU_DS BIT(22)
4160 #define B_BE_IMEM1_WLMCU_DS BIT(21)
4161 #define B_BE_IMEM0_WLMCU_DS BIT(20)
4162 #define B_BE_MEM_BBMCU1_DS BIT(19)
4163 #define B_BE_MEM_BBMCU0_DS_V1 BIT(17)
4164 #define B_BE_MEM_BT_DS BIT(10)
4165 #define B_BE_MEM_SDIO_LS BIT(9)
4166 #define B_BE_MEM_SDIO_DS BIT(8)
4167 #define B_BE_MEM_USB_LS BIT(7)
4168 #define B_BE_MEM_USB_DS BIT(6)
4169 #define B_BE_MEM_PCI_LS BIT(5)
4170 #define B_BE_MEM_PCI_DS BIT(4)
4171 #define B_BE_MEM_WLMAC_LS BIT(3)
4172 
4173 #define R_BE_PCIE_MIO_INTF 0x00E4
4174 #define B_BE_AON_MIO_EPHY_1K_SEL_MASK GENMASK(29, 24)
4175 #define B_BE_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)
4176 #define B_BE_PCIE_MIO_ASIF BIT(15)
4177 #define B_BE_PCIE_MIO_BYIOREG BIT(13)
4178 #define B_BE_PCIE_MIO_RE BIT(12)
4179 #define B_BE_PCIE_MIO_WE_MASK GENMASK(11, 8)
4180 #define B_BE_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
4181 
4182 #define R_BE_PCIE_MIO_INTD 0x00E8
4183 #define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)
4184 
4185 #define R_BE_HALT_H2C_CTRL 0x0160
4186 #define B_BE_HALT_H2C_TRIGGER BIT(0)
4187 
4188 #define R_BE_HALT_C2H_CTRL 0x0164
4189 #define B_BE_HALT_C2H_TRIGGER BIT(0)
4190 
4191 #define R_BE_HALT_H2C 0x0168
4192 #define B_BE_HALT_H2C_MASK GENMASK(31, 0)
4193 
4194 #define R_BE_HALT_C2H 0x016C
4195 #define B_BE_HALT_C2H_ERROR_SENARIO_MASK GENMASK(31, 28)
4196 #define B_BE_ERROR_CODE_MASK GENMASK(15, 0)
4197 
4198 #define R_BE_SYS_CFG5 0x0170
4199 #define B_BE_WDT_DATACPU_WAKE_PCIE_EN BIT(12)
4200 #define B_BE_WDT_DATACPU_WAKE_USB_EN BIT(11)
4201 #define B_BE_WDT_WAKE_PCIE_EN BIT(10)
4202 #define B_BE_WDT_WAKE_USB_EN BIT(9)
4203 #define B_BE_SYM_DIS_HC_ACCESS_MAC BIT(8)
4204 #define B_BE_LPS_STATUS BIT(3)
4205 #define B_BE_HCI_TXDMA_BUSY BIT(2)
4206 
4207 #define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184
4208 
4209 #define R_BE_FWS1IMR 0x0198
4210 #define B_BE_FS_RPWM_INT_EN_V1 BIT(24)
4211 #define B_BE_PCIE_HOTRST_EN BIT(22)
4212 #define B_BE_PCIE_SER_TIMEOUT_INDIC_EN BIT(21)
4213 #define B_BE_PCIE_RXI300_SLVTOUT_INDIC_EN BIT(20)
4214 #define B_BE_AON_PCIE_FLR_INT_EN BIT(19)
4215 #define B_BE_PCIE_ERR_INDIC_INT_EN BIT(18)
4216 #define B_BE_SDIO_ERR_INDIC_INT_EN BIT(17)
4217 #define B_BE_USB_ERR_INDIC_INT_EN BIT(16)
4218 #define B_BE_FS_GPIO27_INT_EN BIT(11)
4219 #define B_BE_FS_GPIO26_INT_EN BIT(10)
4220 #define B_BE_FS_GPIO25_INT_EN BIT(9)
4221 #define B_BE_FS_GPIO24_INT_EN BIT(8)
4222 #define B_BE_FS_GPIO23_INT_EN BIT(7)
4223 #define B_BE_FS_GPIO22_INT_EN BIT(6)
4224 #define B_BE_FS_GPIO21_INT_EN BIT(5)
4225 #define B_BE_FS_GPIO20_INT_EN BIT(4)
4226 #define B_BE_FS_GPIO19_INT_EN BIT(3)
4227 #define B_BE_FS_GPIO18_INT_EN BIT(2)
4228 #define B_BE_FS_GPIO17_INT_EN BIT(1)
4229 #define B_BE_FS_GPIO16_INT_EN BIT(0)
4230 
4231 #define R_BE_HIMR0 0x01A0
4232 #define B_BE_WDT_DATACPU_TIMEOUT_INT_EN BIT(25)
4233 #define B_BE_HALT_D2H_INT_EN BIT(24)
4234 #define B_BE_WDT_TIMEOUT_INT_EN BIT(22)
4235 #define B_BE_HALT_C2H_INT_EN BIT(21)
4236 #define B_BE_RON_INT_EN BIT(20)
4237 #define B_BE_PDNINT_EN BIT(19)
4238 #define B_BE_SPSANA_OCP_INT_EN BIT(18)
4239 #define B_BE_SPS_OCP_INT_EN BIT(17)
4240 #define B_BE_BTON_STS_UPDATE_INT_EN BIT(16)
4241 #define B_BE_GPIOF_INT_EN BIT(15)
4242 #define B_BE_GPIOE_INT_EN BIT(14)
4243 #define B_BE_GPIOD_INT_EN BIT(13)
4244 #define B_BE_GPIOC_INT_EN BIT(12)
4245 #define B_BE_GPIOB_INT_EN BIT(11)
4246 #define B_BE_GPIOA_INT_EN BIT(10)
4247 #define B_BE_GPIO9_INT_EN BIT(9)
4248 #define B_BE_GPIO8_INT_EN BIT(8)
4249 #define B_BE_GPIO7_INT_EN BIT(7)
4250 #define B_BE_GPIO6_INT_EN BIT(6)
4251 #define B_BE_GPIO5_INT_EN BIT(5)
4252 #define B_BE_GPIO4_INT_EN BIT(4)
4253 #define B_BE_GPIO3_INT_EN BIT(3)
4254 #define B_BE_GPIO2_INT_EN BIT(2)
4255 #define B_BE_GPIO1_INT_EN BIT(1)
4256 #define B_BE_GPIO0_INT_EN BIT(0)
4257 
4258 #define R_BE_HISR0 0x01A4
4259 #define B_BE_WDT_DATACPU_TIMEOUT_INT BIT(25)
4260 #define B_BE_HALT_D2H_INT BIT(24)
4261 #define B_BE_WDT_TIMEOUT_INT BIT(22)
4262 #define B_BE_HALT_C2H_INT BIT(21)
4263 #define B_BE_RON_INT BIT(20)
4264 #define B_BE_PDNINT BIT(19)
4265 #define B_BE_SPSANA_OCP_INT BIT(18)
4266 #define B_BE_SPS_OCP_INT BIT(17)
4267 #define B_BE_BTON_STS_UPDATE_INT BIT(16)
4268 #define B_BE_GPIOF_INT BIT(15)
4269 #define B_BE_GPIOE_INT BIT(14)
4270 #define B_BE_GPIOD_INT BIT(13)
4271 #define B_BE_GPIOC_INT BIT(12)
4272 #define B_BE_GPIOB_INT BIT(11)
4273 #define B_BE_GPIOA_INT BIT(10)
4274 #define B_BE_GPIO9_INT BIT(9)
4275 #define B_BE_GPIO8_INT BIT(8)
4276 #define B_BE_GPIO7_INT BIT(7)
4277 #define B_BE_GPIO6_INT BIT(6)
4278 #define B_BE_GPIO5_INT BIT(5)
4279 #define B_BE_GPIO4_INT BIT(4)
4280 #define B_BE_GPIO3_INT BIT(3)
4281 #define B_BE_GPIO2_INT BIT(2)
4282 #define B_BE_GPIO1_INT BIT(1)
4283 #define B_BE_GPIO0_INT BIT(0)
4284 
4285 #define R_BE_WCPU_FW_CTRL 0x01E0
4286 #define B_BE_RUN_ENV_MASK GENMASK(31, 30)
4287 #define B_BE_WCPU_FWDL_STATUS_MASK GENMASK(29, 26)
4288 #define B_BE_WDT_PLT_RST_EN BIT(17)
4289 #define B_BE_FW_SEC_AUTH_DONE BIT(14)
4290 #define B_BE_FW_CPU_UTIL_STS_EN BIT(13)
4291 #define B_BE_BBMCU1_FWDL_EN BIT(12)
4292 #define B_BE_BBMCU0_FWDL_EN BIT(11)
4293 #define B_BE_DATACPU_FWDL_EN BIT(10)
4294 #define B_BE_WLANCPU_FWDL_EN BIT(9)
4295 #define B_BE_WCPU_ROM_CUT_GET BIT(8)
4296 #define B_BE_WCPU_ROM_CUT_VAL_MASK GENMASK(7, 4)
4297 #define B_BE_FW_BOOT_MODE_MASK GENMASK(3, 2)
4298 #define B_BE_H2C_PATH_RDY BIT(1)
4299 #define B_BE_DLFW_PATH_RDY BIT(0)
4300 
4301 #define R_BE_BOOT_REASON 0x01E6
4302 #define B_BE_BOOT_REASON_MASK GENMASK(2, 0)
4303 
4304 #define R_BE_LDM 0x01E8
4305 #define B_BE_EN_32K BIT(31)
4306 #define B_BE_LDM_MASK GENMASK(30, 0)
4307 
4308 #define R_BE_UDM0 0x01F0
4309 #define B_BE_UDM0_SEND2RA_CNT_MASK GENMASK(31, 28)
4310 #define B_BE_UDM0_TX_RPT_CNT_MASK GENMASK(27, 24)
4311 #define B_BE_UDM0_FS_CODE_MASK GENMASK(23, 8)
4312 #define B_BE_NULL_POINTER_INDC BIT(7)
4313 #define B_BE_ROM_ASSERT_INDC BIT(6)
4314 #define B_BE_RAM_ASSERT_INDC BIT(5)
4315 #define B_BE_FW_IMAGE_TYPE BIT(4)
4316 #define B_BE_UDM0_TRAP_LOOP_CTRL BIT(2)
4317 #define B_BE_UDM0_SEND_HALTC2H_CTRL BIT(1)
4318 #define B_BE_UDM0_DBG_MODE_CTRL BIT(0)
4319 
4320 #define R_BE_UDM1 0x01F4
4321 #define B_BE_UDM1_ERROR_ADDR_MASK GENMASK(31, 16)
4322 #define B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)
4323 #define B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)
4324 #define B_BE_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
4325 #define B_BE_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
4326 
4327 #define R_BE_UDM2 0x01F8
4328 #define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
4329 
4330 #define R_BE_AFE_ON_CTRL0 0x0240
4331 #define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29)
4332 #define B_BE_REG_LPF_R2_MASK GENMASK(28, 24)
4333 #define B_BE_REG_LPF_C3_MASK GENMASK(23, 21)
4334 #define B_BE_REG_LPF_C2_MASK GENMASK(20, 18)
4335 #define B_BE_REG_LPF_C1_MASK GENMASK(17, 15)
4336 #define B_BE_REG_CP_ICPX2 BIT(14)
4337 #define B_BE_REG_CP_ICP_SEL_FAST_MASK GENMASK(13, 10)
4338 #define B_BE_REG_CP_ICP_SEL_MASK GENMASK(9, 6)
4339 #define B_BE_REG_IB_PI_MASK GENMASK(5, 4)
4340 #define B_BE_REG_CK_DEBUG_BT BIT(3)
4341 #define B_BE_EN_PC_LDO BIT(2)
4342 #define B_BE_LDO_VSEL_MASK GENMASK(1, 0)
4343 
4344 #define R_BE_AFE_ON_CTRL1 0x0244
4345 #define B_BE_REG_CK_MON_SEL_MASK GENMASK(31, 29)
4346 #define B_BE_REG_CK_MON_CK960M_EN BIT(28)
4347 #define B_BE_REG_XTAL_FREQ_SEL BIT(27)
4348 #define B_BE_REG_XTAL_EDGE_SEL BIT(26)
4349 #define B_BE_REG_VCO_KVCO BIT(25)
4350 #define B_BE_REG_SDM_EDGE_SEL BIT(24)
4351 #define B_BE_REG_SDM_CK_SEL BIT(23)
4352 #define B_BE_REG_SDM_CK_GATED BIT(22)
4353 #define B_BE_REG_PFD_RESET_GATED BIT(21)
4354 #define B_BE_REG_LPF_R3_FAST_MASK GENMASK(20, 16)
4355 #define B_BE_REG_LPF_R2_FAST_MASK GENMASK(15, 11)
4356 #define B_BE_REG_LPF_C3_FAST_MASK GENMASK(10, 8)
4357 #define B_BE_REG_LPF_C2_FAST_MASK GENMASK(7, 5)
4358 #define B_BE_REG_LPF_C1_FAST_MASK GENMASK(4, 2)
4359 #define B_BE_REG_LPF_R3_4_MASK GENMASK(1, 0)
4360 
4361 #define R_BE_AFE_ON_CTRL3 0x024C
4362 #define B_BE_LDO_VSEL_DA_1_MASK GENMASK(31, 30)
4363 #define B_BE_LDO_VSEL_DA_0_MASK GENMASK(29, 28)
4364 #define B_BE_LDO_VSEL_D2S_1_MASK GENMASK(27, 26)
4365 #define B_BE_LDO_VSEL_D2S_0_MASK GENMASK(25, 24)
4366 #define B_BE_LDO_VSEL_BUF_MASK GENMASK(23, 22)
4367 #define B_BE_REG_R2_L_MASK GENMASK(21, 19)
4368 #define B_BE_REG_R1_L_MASK GENMASK(18, 16)
4369 #define B_BE_REG_CK_DEBUG_BT_MON BIT(15)
4370 #define B_BE_REG_BT_CLK_BUF_POWER BIT(14)
4371 #define B_BE_REG_BG_OUT_BTADC_V1 BIT(13)
4372 #define B_BE_REG_SEL_V18 BIT(11)
4373 #define B_BE_REG_FRAC_EN BIT(10)
4374 #define B_BE_REG_CK1920M_EN BIT(9)
4375 #define B_BE_REG_CK1280M_EN BIT(8)
4376 #define B_BE_REG_12LDO_SEL_MASK GENMASK(7, 6)
4377 #define B_BE_REG_09LDO_SEL_MASK GENMASK(5, 4)
4378 #define B_BE_REG_VC_TH BIT(3)
4379 #define B_BE_REG_VC_TL BIT(2)
4380 #define B_BE_REG_CK40M_EN BIT(1)
4381 #define B_BE_REG_CK640M_EN BIT(0)
4382 
4383 #define R_BE_GPIO8_15_FUNC_SEL 0x02D4
4384 #define B_BE_PINMUX_GPIO9_FUNC_SEL_MASK GENMASK(7, 4)
4385 
4386 #define R_BE_WLAN_XTAL_SI_CTRL 0x0270
4387 #define B_BE_WL_XTAL_SI_CMD_POLL BIT(31)
4388 #define B_BE_WL_XTAL_SI_CHIPID_MASK GENMASK(30, 28)
4389 #define B_BE_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
4390 #define B_BE_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
4391 #define B_BE_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
4392 #define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
4393 
4394 #define R_BE_IC_PWR_STATE 0x03F0
4395 #define B_BE_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
4396 #define MAC_AX_SYS_ACT 0x220
4397 #define B_BE_WLMAC_PWR_STE_MASK GENMASK(9, 8)
4398 #define B_BE_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
4399 #define B_BE_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
4400 #define B_BE_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
4401 #define B_BE_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
4402 
4403 #define R_BE_WLCPU_PORT_PC 0x03FC
4404 
4405 #define R_BE_DBG_WOW 0x0504
4406 
4407 #define R_BE_DCPU_PLATFORM_ENABLE 0x0888
4408 #define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10)
4409 #define B_BE_DCPU_WARM_EN BIT(9)
4410 #define B_BE_DCPU_UART_EN BIT(7)
4411 #define B_BE_DCPU_IDDMA_EN BIT(6)
4412 #define B_BE_DCPU_APB_WRAP_EN BIT(2)
4413 #define B_BE_DCPU_EN BIT(1)
4414 #define B_BE_DCPU_PLATFORM_EN BIT(0)
4415 
4416 #define R_BE_PL_AXIDMA_IDCT_MSK 0x0910
4417 #define B_BE_PL_AXIDMA_RRESP_ERR_MASK BIT(6)
4418 #define B_BE_PL_AXIDMA_BRESP_ERR_MASK BIT(5)
4419 #define B_BE_PL_AXIDMA_FC_ERR_MASK BIT(4)
4420 #define B_BE_PL_AXIDMA_TXBD_LEN0_MASK BIT(3)
4421 #define B_BE_PL_AXIDMA_TXBD_4KBOUD_LENERR_MASK BIT(2)
4422 #define B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK BIT(1)
4423 #define B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK BIT(0)
4424 #define B_BE_PL_AXIDMA_IDCT_MSK_CLR (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \
4425 				     B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \
4426 				     B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \
4427 				     B_BE_PL_AXIDMA_FC_ERR_MASK | \
4428 				     B_BE_PL_AXIDMA_BRESP_ERR_MASK | \
4429 				     B_BE_PL_AXIDMA_RRESP_ERR_MASK)
4430 #define B_BE_PL_AXIDMA_IDCT_MSK_SET (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \
4431 				     B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \
4432 				     B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \
4433 				     B_BE_PL_AXIDMA_FC_ERR_MASK)
4434 
4435 #define R_BE_PL_AXIDMA_IDCT 0x0914
4436 #define B_BE_PL_AXIDMA_RRESP_ERR BIT(6)
4437 #define B_BE_PL_AXIDMA_BRESP_ERR BIT(5)
4438 #define B_BE_PL_AXIDMA_FC_ERR BIT(4)
4439 #define B_BE_PL_AXIDMA_TXBD_LEN0 BIT(3)
4440 #define B_BE_PL_AXIDMA_TXBD_4KBOUD_LENERR BIT(2)
4441 #define B_BE_PL_AXIDMA_TXBD_RX_STUCK BIT(1)
4442 #define B_BE_PL_AXIDMA_TXBD_TX_STUCK BIT(0)
4443 
4444 #define R_BE_FILTER_MODEL_ADDR 0x0C04
4445 
4446 #define R_BE_WLAN_WDT 0x3050
4447 #define B_BE_WLAN_WDT_TIMEOUT BIT(31)
4448 #define B_BE_WLAN_WDT_TIMER_CLEAR BIT(4)
4449 #define B_BE_WLAN_WDT_BYPASS BIT(1)
4450 #define B_BE_WLAN_WDT_ENABLE BIT(0)
4451 
4452 #define R_BE_AXIDMA_WDT 0x305C
4453 #define B_BE_AXIDMA_WDT_TIMEOUT BIT(31)
4454 #define B_BE_AXIDMA_WDT_TIMER_CLEAR BIT(4)
4455 #define B_BE_AXIDMA_WDT_BYPASS BIT(1)
4456 #define B_BE_AXIDMA_WDT_ENABLE BIT(0)
4457 
4458 #define R_BE_AON_WDT 0x3068
4459 #define B_BE_AON_WDT_TIMEOUT BIT(31)
4460 #define B_BE_AON_WDT_TIMER_CLEAR BIT(4)
4461 #define B_BE_AON_WDT_BYPASS BIT(1)
4462 #define B_BE_AON_WDT_ENABLE BIT(0)
4463 
4464 #define R_BE_AON_WDT_TMR 0x306C
4465 #define R_BE_MDIO_WDT_TMR 0x3090
4466 #define R_BE_LA_MODE_WDT_TMR 0x309C
4467 #define R_BE_WDT_AR_TMR 0x3144
4468 #define R_BE_WDT_AW_TMR 0x3150
4469 #define R_BE_WLAN_WDT_TMR 0x3054
4470 #define R_BE_WDT_W_TMR 0x315C
4471 #define R_BE_AXIDMA_WDT_TMR 0x3060
4472 #define R_BE_WDT_B_TMR 0x3164
4473 #define R_BE_WDT_R_TMR 0x316C
4474 #define R_BE_LOCAL_WDT_TMR 0x3084
4475 
4476 #define R_BE_LOCAL_WDT 0x3080
4477 #define B_BE_LOCAL_WDT_TIMEOUT BIT(31)
4478 #define B_BE_LOCAL_WDT_TIMER_CLEAR BIT(4)
4479 #define B_BE_LOCAL_WDT_BYPASS BIT(1)
4480 #define B_BE_LOCAL_WDT_ENABLE BIT(0)
4481 
4482 #define R_BE_MDIO_WDT 0x308C
4483 #define B_BE_MDIO_WDT_TIMEOUT BIT(31)
4484 #define B_BE_MDIO_WDT_TIMER_CLEAR BIT(4)
4485 #define B_BE_MDIO_WDT_BYPASS BIT(1)
4486 #define B_BE_MDIO_WDT_ENABLE BIT(0)
4487 
4488 #define R_BE_LA_MODE_WDT 0x3098
4489 #define B_BE_LA_MODE_WDT_TIMEOUT BIT(31)
4490 #define B_BE_LA_MODE_WDT_TIMER_CLEAR BIT(4)
4491 #define B_BE_LA_MODE_WDT_BYPASS BIT(1)
4492 #define B_BE_LA_MODE_WDT_ENABLE BIT(0)
4493 
4494 #define R_BE_WDT_AR 0x3140
4495 #define B_BE_WDT_AR_TIMEOUT BIT(31)
4496 #define B_BE_WDT_AR_TIMER_CLEAR BIT(4)
4497 #define B_BE_WDT_AR_BYPASS BIT(1)
4498 #define B_BE_WDT_AR_ENABLE BIT(0)
4499 
4500 #define R_BE_WDT_AW 0x314C
4501 #define B_BE_WDT_AW_TIMEOUT BIT(31)
4502 #define B_BE_WDT_AW_TIMER_CLEAR BIT(4)
4503 #define B_BE_WDT_AW_BYPASS BIT(1)
4504 #define B_BE_WDT_AW_ENABLE BIT(0)
4505 
4506 #define R_BE_WDT_W 0x3158
4507 #define B_BE_WDT_W_TIMEOUT BIT(31)
4508 #define B_BE_WDT_W_TIMER_CLEAR BIT(4)
4509 #define B_BE_WDT_W_BYPASS BIT(1)
4510 #define B_BE_WDT_W_ENABLE BIT(0)
4511 
4512 #define R_BE_WDT_B 0x3160
4513 #define B_BE_WDT_B_TIMEOUT BIT(31)
4514 #define B_BE_WDT_B_TIMER_CLEAR BIT(4)
4515 #define B_BE_WDT_B_BYPASS BIT(1)
4516 #define B_BE_WDT_B_ENABLE BIT(0)
4517 
4518 #define R_BE_WDT_R 0x3168
4519 #define B_BE_WDT_R_TIMEOUT BIT(31)
4520 #define B_BE_WDT_R_TIMER_CLEAR BIT(4)
4521 #define B_BE_WDT_R_BYPASS BIT(1)
4522 #define B_BE_WDT_R_ENABLE BIT(0)
4523 
4524 #define R_BE_LTR_DECISION_CTRL_V1 0x3610
4525 #define B_BE_ENABLE_LTR_CTL_DECISION BIT(31)
4526 #define B_BE_LAT_LTR_IDX_DRV_VLD_V1 BIT(24)
4527 #define B_BE_LAT_LTR_IDX_DRV_V1_MASK GENMASK(23, 22)
4528 #define B_BE_LAT_LTR_IDX_FW_VLD_V1 BIT(21)
4529 #define B_BE_LAT_LTR_IDX_FW_V1_MASK GENMASK(20, 19)
4530 #define B_BE_LAT_LTR_IDX_HW_VLD_V1 BIT(18)
4531 #define B_BE_LAT_LTR_IDX_HW_V1_MASK GENMASK(17, 16)
4532 #define B_BE_LTR_IDX_DRV_V1_MASK GENMASK(15, 14)
4533 #define B_BE_LTR_REQ_DRV_V1 BIT(13)
4534 #define B_BE_LTR_IDX_DISABLE_V1_MASK GENMASK(9, 8)
4535 #define B_BE_LTR_EN_PORT_V1_MASK GENMASK(6, 4)
4536 #define B_BE_LTR_DRV_DEC_EN_V1 BIT(6)
4537 #define B_BE_LTR_FW_DEC_EN_V1 BIT(5)
4538 #define B_BE_LTR_HW_DEC_EN_V1 BIT(4)
4539 #define B_BE_LTR_SPACE_IDX_MASK GENMASK(1, 0)
4540 
4541 #define R_BE_LTR_LATENCY_IDX0_V1 0x3614
4542 #define R_BE_LTR_LATENCY_IDX1_V1 0x3618
4543 #define R_BE_LTR_LATENCY_IDX2_V1 0x361C
4544 #define R_BE_LTR_LATENCY_IDX3_V1 0x3620
4545 
4546 #define R_BE_H2CREG_DATA0 0x7140
4547 #define R_BE_H2CREG_DATA1 0x7144
4548 #define R_BE_H2CREG_DATA2 0x7148
4549 #define R_BE_H2CREG_DATA3 0x714C
4550 #define R_BE_C2HREG_DATA0 0x7150
4551 #define R_BE_C2HREG_DATA1 0x7154
4552 #define R_BE_C2HREG_DATA2 0x7158
4553 #define R_BE_C2HREG_DATA3 0x715C
4554 #define R_BE_H2CREG_CTRL 0x7160
4555 #define B_BE_H2CREG_TRIGGER BIT(0)
4556 #define R_BE_C2HREG_CTRL 0x7164
4557 #define B_BE_C2HREG_TRIGGER BIT(0)
4558 
4559 #define R_BE_HCI_FUNC_EN 0x7880
4560 #define B_BE_HCI_CR_PROTECT BIT(31)
4561 #define B_BE_HCI_TRXBUF_EN BIT(2)
4562 #define B_BE_HCI_RXDMA_EN BIT(1)
4563 #define B_BE_HCI_TXDMA_EN BIT(0)
4564 
4565 #define R_BE_DBG_WOW_READY 0x815E
4566 #define B_BE_DBG_WOW_READY GENMASK(7, 0)
4567 
4568 #define R_BE_DMAC_FUNC_EN 0x8400
4569 #define B_BE_DMAC_CRPRT BIT(31)
4570 #define B_BE_MAC_FUNC_EN BIT(30)
4571 #define B_BE_DMAC_FUNC_EN BIT(29)
4572 #define B_BE_MPDU_PROC_EN BIT(28)
4573 #define B_BE_WD_RLS_EN BIT(27)
4574 #define B_BE_DLE_WDE_EN BIT(26)
4575 #define B_BE_TXPKT_CTRL_EN BIT(25)
4576 #define B_BE_STA_SCH_EN BIT(24)
4577 #define B_BE_DLE_PLE_EN BIT(23)
4578 #define B_BE_PKT_BUF_EN BIT(22)
4579 #define B_BE_DMAC_TBL_EN BIT(21)
4580 #define B_BE_PKT_IN_EN BIT(20)
4581 #define B_BE_DLE_CPUIO_EN BIT(19)
4582 #define B_BE_DISPATCHER_EN BIT(18)
4583 #define B_BE_BBRPT_EN BIT(17)
4584 #define B_BE_MAC_SEC_EN BIT(16)
4585 #define B_BE_DMACREG_GCKEN BIT(15)
4586 #define B_BE_H_AXIDMA_EN BIT(14)
4587 #define B_BE_DMAC_MLO_EN BIT(11)
4588 #define B_BE_PLRLS_EN BIT(10)
4589 #define B_BE_P_AXIDMA_EN BIT(9)
4590 #define B_BE_DLE_DATACPUIO_EN BIT(8)
4591 #define B_BE_LTR_CTL_EN BIT(7)
4592 
4593 #define R_BE_DMAC_CLK_EN 0x8404
4594 #define B_BE_MAC_CKEN BIT(30)
4595 #define B_BE_DMAC_CKEN BIT(29)
4596 #define B_BE_MPDU_CKEN BIT(28)
4597 #define B_BE_WD_RLS_CLK_EN BIT(27)
4598 #define B_BE_DLE_WDE_CLK_EN BIT(26)
4599 #define B_BE_TXPKT_CTRL_CLK_EN BIT(25)
4600 #define B_BE_STA_SCH_CLK_EN BIT(24)
4601 #define B_BE_DLE_PLE_CLK_EN BIT(23)
4602 #define B_BE_PKTBUF_CKEN BIT(22)
4603 #define B_BE_DMAC_TABLE_CLK_EN BIT(21)
4604 #define B_BE_PKT_IN_CLK_EN BIT(20)
4605 #define B_BE_DLE_CPUIO_CLK_EN BIT(19)
4606 #define B_BE_DISPATCHER_CLK_EN BIT(18)
4607 #define B_BE_BBRPT_CLK_EN BIT(17)
4608 #define B_BE_MAC_SEC_CLK_EN BIT(16)
4609 #define B_BE_H_AXIDMA_CKEN BIT(14)
4610 #define B_BE_DMAC_MLO_CKEN BIT(11)
4611 #define B_BE_PLRLS_CKEN BIT(10)
4612 #define B_BE_P_AXIDMA_CKEN BIT(9)
4613 #define B_BE_DLE_DATACPUIO_CKEN BIT(8)
4614 
4615 #define R_BE_LTR_CTRL_0 0x8410
4616 #define B_BE_LTR_REQ_FW BIT(18)
4617 #define B_BE_LTR_IDX_FW_MASK GENMASK(17, 16)
4618 #define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
4619 #define B_BE_LTR_WD_NOEMP_CHK BIT(1)
4620 #define B_BE_LTR_HW_EN BIT(0)
4621 
4622 #define R_BE_LTR_CFG_0 0x8414
4623 #define B_BE_LTR_IDX_DISABLE_MASK GENMASK(17, 16)
4624 #define B_BE_LTR_IDX_IDLE_MASK GENMASK(15, 14)
4625 #define B_BE_LTR_IDX_ACTIVE_MASK GENMASK(13, 12)
4626 #define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
4627 #define B_BE_EN_LTR_CMAC_RX_USE_PG_CHK BIT(3)
4628 #define B_BE_EN_LTR_WD_NON_EMPTY_CHK BIT(2)
4629 #define B_BE_EN_LTR_HAXIDMA_TX_IDLE_CHK BIT(1)
4630 #define B_BE_EN_LTR_HAXIDMA_RX_IDLE_CHK BIT(0)
4631 
4632 #define R_BE_LTR_CFG_1 0x8418
4633 #define B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK GENMASK(27, 16)
4634 #define B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK GENMASK(11, 0)
4635 
4636 #define R_BE_DMAC_TABLE_CTRL 0x8420
4637 #define B_BE_HWAMSDU_PADDING_MODE BIT(31)
4638 #define B_BE_MACID_MPDU_PROCESSOR_OFFSET_MASK GENMASK(26, 16)
4639 #define B_BE_DMAC_ADDR_MODE BIT(12)
4640 #define B_BE_DMAC_CTRL_INFO_SER_IO BIT(11)
4641 #define B_BE_DMAC_CTRL_INFO_OFFSET_MASK GENMASK(10, 0)
4642 
4643 #define R_BE_SER_DBG_INFO 0x8424
4644 #define B_BE_SER_L0_PROMOTE_L1_EVENT_MASK GENMASK(31, 28)
4645 #define B_BE_SER_L1_COUNTER_MASK GENMASK(27, 24)
4646 #define B_BE_RMAC_PPDU_HANG_CNT_MASK GENMASK(23, 16)
4647 #define B_BE_SER_L0_COUNTER_MASK GENMASK(8, 0)
4648 
4649 #define R_BE_DMAC_SYS_CR32B 0x842C
4650 #define B_BE_DMAC_BB_PHY1_MASK GENMASK(31, 16)
4651 #define B_BE_DMAC_BB_PHY0_MASK GENMASK(15, 0)
4652 #define B_BE_DMAC_BB_CTRL_39 BIT(31)
4653 #define B_BE_DMAC_BB_CTRL_38 BIT(30)
4654 #define B_BE_DMAC_BB_CTRL_37 BIT(29)
4655 #define B_BE_DMAC_BB_CTRL_36 BIT(28)
4656 #define B_BE_DMAC_BB_CTRL_35 BIT(27)
4657 #define B_BE_DMAC_BB_CTRL_34 BIT(26)
4658 #define B_BE_DMAC_BB_CTRL_33 BIT(25)
4659 #define B_BE_DMAC_BB_CTRL_32 BIT(24)
4660 #define B_BE_DMAC_BB_CTRL_31 BIT(23)
4661 #define B_BE_DMAC_BB_CTRL_30 BIT(22)
4662 #define B_BE_DMAC_BB_CTRL_29 BIT(21)
4663 #define B_BE_DMAC_BB_CTRL_28 BIT(20)
4664 #define B_BE_DMAC_BB_CTRL_27 BIT(19)
4665 #define B_BE_DMAC_BB_CTRL_26 BIT(18)
4666 #define B_BE_DMAC_BB_CTRL_25 BIT(17)
4667 #define B_BE_DMAC_BB_CTRL_24 BIT(16)
4668 #define B_BE_DMAC_BB_CTRL_23 BIT(15)
4669 #define B_BE_DMAC_BB_CTRL_22 BIT(14)
4670 #define B_BE_DMAC_BB_CTRL_21 BIT(13)
4671 #define B_BE_DMAC_BB_CTRL_20 BIT(12)
4672 #define B_BE_DMAC_BB_CTRL_19 BIT(11)
4673 #define B_BE_DMAC_BB_CTRL_18 BIT(10)
4674 #define B_BE_DMAC_BB_CTRL_17 BIT(9)
4675 #define B_BE_DMAC_BB_CTRL_16 BIT(8)
4676 #define B_BE_DMAC_BB_CTRL_15 BIT(7)
4677 #define B_BE_DMAC_BB_CTRL_14 BIT(6)
4678 #define B_BE_DMAC_BB_CTRL_13 BIT(5)
4679 #define B_BE_DMAC_BB_CTRL_12 BIT(4)
4680 #define B_BE_DMAC_BB_CTRL_11 BIT(3)
4681 #define B_BE_DMAC_BB_CTRL_10 BIT(2)
4682 #define B_BE_DMAC_BB_CTRL_9 BIT(1)
4683 #define B_BE_DMAC_BB_CTRL_8 BIT(0)
4684 
4685 #define R_BE_DLE_EMPTY0 0x8430
4686 #define B_BE_PLE_EMPTY_QTA_DMAC_H2D BIT(27)
4687 #define B_BE_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26)
4688 #define B_BE_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25)
4689 #define B_BE_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
4690 #define B_BE_PLE_EMPTY_QTA_DMAC_H2C BIT(23)
4691 #define B_BE_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22)
4692 #define B_BE_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21)
4693 #define B_BE_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20)
4694 #define B_BE_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19)
4695 #define B_BE_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18)
4696 #define B_BE_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17)
4697 #define B_BE_WDE_EMPTY_QTA_DMAC_HIF BIT(16)
4698 #define B_BE_WDE_EMPTY_QUE_CMAC_B1_HIQ BIT(15)
4699 #define B_BE_WDE_EMPTY_QUE_CMAC_B1_MBH BIT(14)
4700 #define B_BE_WDE_EMPTY_QUE_CMAC_B0_OTHERS BIT(13)
4701 #define B_BE_WDE_EMPTY_QUE_DMAC_MLO_ACQ BIT(12)
4702 #define B_BE_WDE_EMPTY_QUE_DMAC_MLO_MISC BIT(11)
4703 #define B_BE_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10)
4704 #define B_BE_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
4705 #define B_BE_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8)
4706 #define B_BE_WDE_EMPTY_QUE_OTHERS BIT(7)
4707 #define B_BE_WDE_EMPTY_QUE_CMAC_WMM3 BIT(6)
4708 #define B_BE_WDE_EMPTY_QUE_CMAC_WMM2 BIT(5)
4709 #define B_BE_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
4710 #define B_BE_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3)
4711 #define B_BE_WDE_EMPTY_QUE_CMAC1_MBH BIT(2)
4712 #define B_BE_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
4713 #define B_BE_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
4714 
4715 #define R_BE_DLE_EMPTY1 0x8434
4716 #define B_BE_PLE_EMPTY_QTA_CMAC_DMA_TXRPT BIT(21)
4717 #define B_BE_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20)
4718 #define B_BE_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19)
4719 #define B_BE_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18)
4720 #define B_BE_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17)
4721 #define B_BE_PLE_EMPTY_QTA_DMAC_C2H BIT(16)
4722 #define B_BE_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5)
4723 #define B_BE_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
4724 #define B_BE_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3)
4725 #define B_BE_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2)
4726 #define B_BE_PLE_EMPTY_QUE_DMAC_HDP BIT(1)
4727 #define B_BE_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
4728 
4729 #define R_BE_SER_L1_DBG_CNT_0 0x8440
4730 #define B_BE_SER_L1_WDRLS_CNT_MASK GENMASK(31, 24)
4731 #define B_BE_SER_L1_SEC_CNT_MASK GENMASK(23, 16)
4732 #define B_BE_SER_L1_MPDU_CNT_MASK GENMASK(15, 8)
4733 #define B_BE_SER_L1_STA_SCH_CNT_MASK GENMASK(7, 0)
4734 
4735 #define R_BE_SER_L1_DBG_CNT_1 0x8444
4736 #define B_BE_SER_L1_WDE_CNT_MASK GENMASK(31, 24)
4737 #define B_BE_SER_L1_TXPKTCTRL_CNT_MASK GENMASK(23, 16)
4738 #define B_BE_SER_L1_PLE_CNT_MASK GENMASK(15, 8)
4739 #define B_BE_SER_L1_PKTIN_CNT_MASK GENMASK(7, 0)
4740 
4741 #define R_BE_SER_L1_DBG_CNT_2 0x8448
4742 #define B_BE_SER_L1_DISP_CNT_MASK GENMASK(31, 24)
4743 #define B_BE_SER_L1_APB_BRIDGE_CNT_MASK GENMASK(23, 16)
4744 #define B_BE_SER_L1_DLE_W_CPUIO_CNT_MASK GENMASK(15, 8)
4745 #define B_BE_SER_L1_BBRPT_CNT_MASK GENMASK(7, 0)
4746 
4747 #define R_BE_SER_L1_DBG_CNT_3 0x844C
4748 #define B_BE_SER_L1_HCI_BUF_CNT_MASK GENMASK(31, 24)
4749 #define B_BE_SER_L1_P_AXIDMA_CNT_MASK GENMASK(23, 16)
4750 #define B_BE_SER_L1_H_AXIDMA_CNT_MASK GENMASK(15, 8)
4751 #define B_BE_SER_L1_MLO_ERR_CNT_MASK GENMASK(7, 0)
4752 
4753 #define R_BE_SER_L1_DBG_CNT_4 0x8450
4754 #define B_BE_SER_L1_PLDRLS_ERR_CNT_MASK GENMASK(31, 24)
4755 #define B_BE_SER_L1_DLE_D_CPUIO_CNT_MASK GENMASK(23, 16)
4756 
4757 #define R_BE_SER_L1_DBG_CNT_5 0x8454
4758 #define B_BE_SER_L1_DBG_0_MASK GENMASK(31, 0)
4759 
4760 #define R_BE_SER_L1_DBG_CNT_6 0x8458
4761 #define B_BE_SER_L1_DBG_1_MASK GENMASK(31, 0)
4762 
4763 #define R_BE_SER_L1_DBG_CNT_7 0x845C
4764 #define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0)
4765 
4766 #define R_BE_DMAC_ERR_IMR 0x8520
4767 #define B_BE_DMAC_NOTX_ERR_INT_EN BIT(21)
4768 #define B_BE_DMAC_NORX_ERR_INT_EN BIT(20)
4769 #define B_BE_DLE_DATACPUIO_ERR_INT_EN BIT(19)
4770 #define B_BE_PLRSL_ERR_INT_EN BIT(18)
4771 #define B_BE_MLO_ERR_INT_EN BIT(17)
4772 #define B_BE_DMAC_FW_ERR_INT_EN BIT(16)
4773 #define B_BE_H_AXIDMA_ERR_INT_EN BIT(14)
4774 #define B_BE_P_AXIDMA_ERR_INT_EN BIT(13)
4775 #define B_BE_HCI_BUF_ERR_INT_EN BIT(12)
4776 #define B_BE_BBRPT_ERR_INT_EN BIT(11)
4777 #define B_BE_DLE_CPUIO_ERR_INT_EN BIT(10)
4778 #define B_BE_APB_BRIDGE_ERR_INT_EN BIT(9)
4779 #define B_BE_DISPATCH_ERR_INT_EN BIT(8)
4780 #define B_BE_PKTIN_ERR_INT_EN BIT(7)
4781 #define B_BE_PLE_DLE_ERR_INT_EN BIT(6)
4782 #define B_BE_TXPKTCTRL_ERR_INT_EN BIT(5)
4783 #define B_BE_WDE_DLE_ERR_INT_EN BIT(4)
4784 #define B_BE_STA_SCHEDULER_ERR_INT_EN BIT(3)
4785 #define B_BE_MPDU_ERR_INT_EN BIT(2)
4786 #define B_BE_WSEC_ERR_INT_EN BIT(1)
4787 #define B_BE_WDRLS_ERR_INT_EN BIT(0)
4788 
4789 #define R_BE_DMAC_ERR_ISR 0x8524
4790 #define B_BE_DLE_DATACPUIO_ERR_INT BIT(19)
4791 #define B_BE_PLRLS_ERR_INT BIT(18)
4792 #define B_BE_MLO_ERR_INT BIT(17)
4793 #define B_BE_DMAC_FW_ERR_IDCT BIT(16)
4794 #define B_BE_H_AXIDMA_ERR_INT BIT(14)
4795 #define B_BE_P_AXIDMA_ERR_INT BIT(13)
4796 #define B_BE_HCI_BUF_ERR_FLAG BIT(12)
4797 #define B_BE_BBRPT_ERR_FLAG BIT(11)
4798 #define B_BE_DLE_CPUIO_ERR_FLAG BIT(10)
4799 #define B_BE_APB_BRIDGE_ERR_FLAG BIT(9)
4800 #define B_BE_DISPATCH_ERR_FLAG BIT(8)
4801 #define B_BE_PKTIN_ERR_FLAG BIT(7)
4802 #define B_BE_PLE_DLE_ERR_FLAG BIT(6)
4803 #define B_BE_TXPKTCTRL_ERR_FLAG BIT(5)
4804 #define B_BE_WDE_DLE_ERR_FLAG BIT(4)
4805 #define B_BE_STA_SCHEDULER_ERR_FLAG BIT(3)
4806 #define B_BE_MPDU_ERR_FLAG BIT(2)
4807 #define B_BE_WSEC_ERR_FLAG BIT(1)
4808 #define B_BE_WDRLS_ERR_FLAG BIT(0)
4809 
4810 #define R_BE_DISP_ERROR_ISR0 0x8804
4811 #define B_BE_REUSE_SIZE_ERR BIT(31)
4812 #define B_BE_REUSE_EN_ERR BIT(30)
4813 #define B_BE_STF_OQT_UNDERFLOW_ERR BIT(29)
4814 #define B_BE_STF_OQT_OVERFLOW_ERR BIT(28)
4815 #define B_BE_STF_WRFF_UNDERFLOW_ERR BIT(27)
4816 #define B_BE_STF_WRFF_OVERFLOW_ERR BIT(26)
4817 #define B_BE_STF_CMD_UNDERFLOW_ERR BIT(25)
4818 #define B_BE_STF_CMD_OVERFLOW_ERR BIT(24)
4819 #define B_BE_REUSE_SIZE_ZERO_ERR BIT(23)
4820 #define B_BE_REUSE_PKT_CNT_ERR BIT(22)
4821 #define B_BE_CDT_PTR_TIMEOUT_ERR BIT(21)
4822 #define B_BE_CDT_HCI_TIMEOUT_ERR BIT(20)
4823 #define B_BE_HDT_PTR_TIMEOUT_ERR BIT(19)
4824 #define B_BE_HDT_HCI_TIMEOUT_ERR BIT(18)
4825 #define B_BE_CDT_ADDR_INFO_LEN_ERR BIT(17)
4826 #define B_BE_HDT_ADDR_INFO_LEN_ERR BIT(16)
4827 #define B_BE_CDR_DMA_TIMEOUT_ERR BIT(15)
4828 #define B_BE_CDR_RX_TIMEOUT_ERR BIT(14)
4829 #define B_BE_PLE_OUTPUT_ERR BIT(12)
4830 #define B_BE_PLE_RESPOSE_ERR BIT(11)
4831 #define B_BE_PLE_BURST_NUM_ERR BIT(10)
4832 #define B_BE_PLE_NULL_PKT_ERR BIT(9)
4833 #define B_BE_PLE_FLOW_CTRL_ERR BIT(8)
4834 #define B_BE_HDR_DMA_TIMEOUT_ERR BIT(7)
4835 #define B_BE_HDR_RX_TIMEOUT_ERR BIT(6)
4836 #define B_BE_WDE_OUTPUT_ERR BIT(4)
4837 #define B_BE_WDE_RESPONSE_ERR BIT(3)
4838 #define B_BE_WDE_BURST_NUM_ERR BIT(2)
4839 #define B_BE_WDE_NULL_PKT_ERR BIT(1)
4840 #define B_BE_WDE_FLOW_CTRL_ERR BIT(0)
4841 
4842 #define R_BE_DISP_ERROR_ISR1 0x8808
4843 #define B_BE_HR_WRFF_UNDERFLOW_ERR BIT(31)
4844 #define B_BE_HR_WRFF_OVERFLOW_ERR BIT(30)
4845 #define B_BE_HR_CHKSUM_FSM_ERR BIT(29)
4846 #define B_BE_HR_SHIFT_DMA_CFG_ERR BIT(28)
4847 #define B_BE_HR_DMA_PROCESS_ERR BIT(27)
4848 #define B_BE_HR_TOTAL_LEN_UNDER_ERR BIT(26)
4849 #define B_BE_HR_SHIFT_EN_ERR BIT(25)
4850 #define B_BE_HR_AGG_CFG_ERR BIT(24)
4851 #define B_BE_HR_PLD_LEN_ZERO_ERR BIT(22)
4852 #define B_BE_HT_ILL_CH_ERR BIT(20)
4853 #define B_BE_HT_ADDR_INFO_LEN_ERR BIT(18)
4854 #define B_BE_HT_WD_LEN_OVER_ERR BIT(17)
4855 #define B_BE_HT_PLD_CMD_UNDERFLOW_ERR BIT(16)
4856 #define B_BE_HT_PLD_CMD_OVERFLOW_ERR BIT(15)
4857 #define B_BE_HT_WRFF_UNDERFLOW_ERR BIT(14)
4858 #define B_BE_HT_WRFF_OVERFLOW_ERR BIT(13)
4859 #define B_BE_HT_CHKSUM_FSM_ERR BIT(12)
4860 #define B_BE_HT_NON_IDLE_PKT_STR_ERR BIT(11)
4861 #define B_BE_HT_PRE_SUB_BE_ERR BIT(10)
4862 #define B_BE_HT_WD_CHKSUM_ERR BIT(9)
4863 #define B_BE_HT_CHANNEL_DMA_ERR BIT(8)
4864 #define B_BE_HT_OFFSET_UNMATCH_ERR BIT(7)
4865 #define B_BE_HT_PAYLOAD_UNDER_ERR BIT(6)
4866 #define B_BE_HT_PAYLOAD_OVER_ERR BIT(5)
4867 #define B_BE_HT_PERMU_FF_UNDERFLOW_ERR BIT(4)
4868 #define B_BE_HT_PERMU_FF_OVERFLOW_ERR BIT(3)
4869 #define B_BE_HT_PKT_FAIL_ERR BIT(2)
4870 #define B_BE_HT_CH_ID_ERR BIT(1)
4871 #define B_BE_HT_EP_CH_DIFF_ERR BIT(0)
4872 
4873 #define R_BE_DISP_ERROR_ISR2 0x880C
4874 #define B_BE_CR_PLD_LEN_ERR BIT(30)
4875 #define B_BE_CR_WRFF_UNDERFLOW_ERR BIT(29)
4876 #define B_BE_CR_WRFF_OVERFLOW_ERR BIT(28)
4877 #define B_BE_CR_SHIFT_DMA_CFG_ERR BIT(27)
4878 #define B_BE_CR_DMA_PROCESS_ERR BIT(26)
4879 #define B_BE_CR_SHIFT_EN_ERR BIT(24)
4880 #define B_BE_REUSE_FIFO_B_UNDER_ERR BIT(22)
4881 #define B_BE_REUSE_FIFO_B_OVER_ERR BIT(21)
4882 #define B_BE_REUSE_FIFO_A_UNDER_ERR BIT(20)
4883 #define B_BE_REUSE_FIFO_A_OVER_ERR BIT(19)
4884 #define B_BE_CT_ADDR_INFO_LEN_MISS_ERR BIT(17)
4885 #define B_BE_CT_WD_LEN_OVER_ERR BIT(16)
4886 #define B_BE_CT_F2P_SEQ_ERR BIT(15)
4887 #define B_BE_CT_F2P_QSEL_ERR BIT(14)
4888 #define B_BE_CT_PLD_CMD_UNDERFLOW_ERR BIT(13)
4889 #define B_BE_CT_PLD_CMD_OVERFLOW_ERR BIT(12)
4890 #define B_BE_CT_PRE_SUB_ERR BIT(11)
4891 #define B_BE_CT_WD_CHKSUM_ERR BIT(10)
4892 #define B_BE_CT_CHANNEL_DMA_ERR BIT(9)
4893 #define B_BE_CT_OFFSET_UNMATCH_ERR BIT(8)
4894 #define B_BE_F2P_TOTAL_NUM_ERR BIT(7)
4895 #define B_BE_CT_PAYLOAD_UNDER_ERR BIT(6)
4896 #define B_BE_CT_PAYLOAD_OVER_ERR BIT(5)
4897 #define B_BE_CT_PERMU_FF_UNDERFLOW_ERR BIT(4)
4898 #define B_BE_CT_PERMU_FF_OVERFLOW_ERR BIT(3)
4899 #define B_BE_CT_CH_ID_ERR BIT(2)
4900 #define B_BE_CT_EP_CH_DIFF_ERR BIT(0)
4901 
4902 #define R_BE_DISP_OTHER_IMR 0x8870
4903 #define B_BE_REUSE_SIZE_ERR_INT_EN BIT(31)
4904 #define B_BE_REUSE_EN_ERR_INT_EN BIT(30)
4905 #define B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29)
4906 #define B_BE_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28)
4907 #define B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27)
4908 #define B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26)
4909 #define B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25)
4910 #define B_BE_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
4911 #define B_BE_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23)
4912 #define B_BE_REUSE_PKT_CNT_ERR_INT_EN BIT(22)
4913 #define B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21)
4914 #define B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20)
4915 #define B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19)
4916 #define B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18)
4917 #define B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17)
4918 #define B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16)
4919 #define B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15)
4920 #define B_BE_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14)
4921 #define B_BE_PLE_OUTPUT_ERR_INT_EN BIT(12)
4922 #define B_BE_PLE_RESPOSE_ERR_INT_EN BIT(11)
4923 #define B_BE_PLE_BURST_NUM_ERR_INT_EN BIT(10)
4924 #define B_BE_PLE_NULL_PKT_ERR_INT_EN BIT(9)
4925 #define B_BE_PLE_FLOW_CTRL_ERR_INT_EN BIT(8)
4926 #define B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
4927 #define B_BE_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6)
4928 #define B_BE_WDE_OUTPUT_ERR_INT_EN BIT(4)
4929 #define B_BE_WDE_RESPONSE_ERR_INT_EN BIT(3)
4930 #define B_BE_WDE_BURST_NUM_ERR_INT_EN BIT(2)
4931 #define B_BE_WDE_NULL_PKT_ERR_INT_EN BIT(1)
4932 #define B_BE_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
4933 #define B_BE_DISP_OTHER_IMR_CLR (B_BE_WDE_FLOW_CTRL_ERR_INT_EN | \
4934 				 B_BE_WDE_NULL_PKT_ERR_INT_EN | \
4935 				 B_BE_WDE_BURST_NUM_ERR_INT_EN | \
4936 				 B_BE_WDE_RESPONSE_ERR_INT_EN | \
4937 				 B_BE_WDE_OUTPUT_ERR_INT_EN | \
4938 				 B_BE_HDR_RX_TIMEOUT_ERR_INT_EN | \
4939 				 B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN | \
4940 				 B_BE_PLE_FLOW_CTRL_ERR_INT_EN | \
4941 				 B_BE_PLE_NULL_PKT_ERR_INT_EN | \
4942 				 B_BE_PLE_BURST_NUM_ERR_INT_EN | \
4943 				 B_BE_PLE_RESPOSE_ERR_INT_EN | \
4944 				 B_BE_PLE_OUTPUT_ERR_INT_EN | \
4945 				 B_BE_CDR_RX_TIMEOUT_ERR_INT_EN | \
4946 				 B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN | \
4947 				 B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN | \
4948 				 B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN | \
4949 				 B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN | \
4950 				 B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN | \
4951 				 B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN | \
4952 				 B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN | \
4953 				 B_BE_REUSE_PKT_CNT_ERR_INT_EN | \
4954 				 B_BE_REUSE_SIZE_ZERO_ERR_INT_EN | \
4955 				 B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \
4956 				 B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \
4957 				 B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \
4958 				 B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
4959 				 B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \
4960 				 B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN | \
4961 				 B_BE_REUSE_EN_ERR_INT_EN | \
4962 				 B_BE_REUSE_SIZE_ERR_INT_EN)
4963 #define B_BE_DISP_OTHER_IMR_SET (B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \
4964 				 B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \
4965 				 B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \
4966 				 B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
4967 				 B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \
4968 				 B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN)
4969 
4970 #define R_BE_DISP_HOST_IMR 0x8874
4971 #define B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
4972 #define B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30)
4973 #define B_BE_HR_CHKSUM_FSM_ERR_INT_EN BIT(29)
4974 #define B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
4975 #define B_BE_HR_DMA_PROCESS_ERR_INT_EN BIT(27)
4976 #define B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26)
4977 #define B_BE_HR_SHIFT_EN_ERR_INT_EN BIT(25)
4978 #define B_BE_HR_AGG_CFG_ERR_INT_EN BIT(24)
4979 #define B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22)
4980 #define B_BE_HT_ILL_CH_ERR_INT_EN BIT(20)
4981 #define B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18)
4982 #define B_BE_HT_WD_LEN_OVER_ERR_INT_EN BIT(17)
4983 #define B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16)
4984 #define B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15)
4985 #define B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14)
4986 #define B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13)
4987 #define B_BE_HT_CHKSUM_FSM_ERR_INT_EN BIT(12)
4988 #define B_BE_HT_NON_IDLE_PKT_STR_ERR_EN BIT(11)
4989 #define B_BE_HT_PRE_SUB_ERR_INT_EN BIT(10)
4990 #define B_BE_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
4991 #define B_BE_HT_CHANNEL_DMA_ERR_INT_EN BIT(8)
4992 #define B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
4993 #define B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
4994 #define B_BE_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
4995 #define B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
4996 #define B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
4997 #define B_BE_HT_PKT_FAIL_ERR_INT_EN BIT(2)
4998 #define B_BE_HT_CH_ID_ERR_INT_EN BIT(1)
4999 #define B_BE_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
5000 #define B_BE_DISP_HOST_IMR_CLR (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \
5001 				B_BE_HT_CH_ID_ERR_INT_EN | \
5002 				B_BE_HT_PKT_FAIL_ERR_INT_EN | \
5003 				B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5004 				B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5005 				B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \
5006 				B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \
5007 				B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN | \
5008 				B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \
5009 				B_BE_HT_WD_CHKSUM_ERR_INT_EN | \
5010 				B_BE_HT_PRE_SUB_ERR_INT_EN | \
5011 				B_BE_HT_NON_IDLE_PKT_STR_ERR_EN | \
5012 				B_BE_HT_CHKSUM_FSM_ERR_INT_EN | \
5013 				B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \
5014 				B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
5015 				B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5016 				B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5017 				B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \
5018 				B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN | \
5019 				B_BE_HT_ILL_CH_ERR_INT_EN | \
5020 				B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN | \
5021 				B_BE_HR_AGG_CFG_ERR_INT_EN | \
5022 				B_BE_HR_SHIFT_EN_ERR_INT_EN | \
5023 				B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
5024 				B_BE_HR_DMA_PROCESS_ERR_INT_EN | \
5025 				B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN | \
5026 				B_BE_HR_CHKSUM_FSM_ERR_INT_EN | \
5027 				B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \
5028 				B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN)
5029 #define B_BE_DISP_HOST_IMR_SET (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \
5030 				B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5031 				B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5032 				B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \
5033 				B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \
5034 				B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \
5035 				B_BE_HT_PRE_SUB_ERR_INT_EN | \
5036 				B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \
5037 				B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
5038 				B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5039 				B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5040 				B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \
5041 				B_BE_HT_ILL_CH_ERR_INT_EN | \
5042 				B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
5043 				B_BE_HR_DMA_PROCESS_ERR_INT_EN | \
5044 				B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \
5045 				B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN)
5046 
5047 #define R_BE_DISP_CPU_IMR 0x8878
5048 #define B_BE_CR_PLD_LEN_ERR_INT_EN BIT(30)
5049 #define B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29)
5050 #define B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28)
5051 #define B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27)
5052 #define B_BE_CR_DMA_PROCESS_ERR_INT_EN BIT(26)
5053 #define B_BE_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25)
5054 #define B_BE_CR_SHIFT_EN_ERR_INT_EN BIT(24)
5055 #define B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22)
5056 #define B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21)
5057 #define B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20)
5058 #define B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19)
5059 #define B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17)
5060 #define B_BE_CT_WD_LEN_OVER_ERR_INT_EN BIT(16)
5061 #define B_BE_CT_F2P_SEQ_ERR_INT_EN BIT(15)
5062 #define B_BE_CT_F2P_QSEL_ERR_INT_EN BIT(14)
5063 #define B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13)
5064 #define B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12)
5065 #define B_BE_CT_PRE_SUB_ERR_INT_EN BIT(11)
5066 #define B_BE_CT_WD_CHKSUM_ERR_INT_EN BIT(10)
5067 #define B_BE_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
5068 #define B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8)
5069 #define B_BE_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
5070 #define B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
5071 #define B_BE_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
5072 #define B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
5073 #define B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
5074 #define B_BE_CT_CH_ID_ERR_INT_EN BIT(2)
5075 #define B_BE_CT_PKT_FAIL_ERR_INT_EN BIT(1)
5076 #define B_BE_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
5077 #define B_BE_DISP_CPU_IMR_CLR (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \
5078 			       B_BE_CT_CH_ID_ERR_INT_EN | \
5079 			       B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5080 			       B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5081 			       B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \
5082 			       B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \
5083 			       B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN | \
5084 			       B_BE_CT_CHANNEL_DMA_ERR_INT_EN | \
5085 			       B_BE_CT_WD_CHKSUM_ERR_INT_EN | \
5086 			       B_BE_CT_PRE_SUB_ERR_INT_EN | \
5087 			       B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5088 			       B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5089 			       B_BE_CT_F2P_QSEL_ERR_INT_EN | \
5090 			       B_BE_CT_F2P_SEQ_ERR_INT_EN | \
5091 			       B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \
5092 			       B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \
5093 			       B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \
5094 			       B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
5095 			       B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \
5096 			       B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
5097 			       B_BE_CR_SHIFT_EN_ERR_INT_EN | \
5098 			       B_BE_CR_DMA_PROCESS_ERR_INT_EN | \
5099 			       B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN | \
5100 			       B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
5101 			       B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN | \
5102 			       B_BE_CR_PLD_LEN_ERR_INT_EN)
5103 #define B_BE_DISP_CPU_IMR_SET (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \
5104 			       B_BE_CT_CH_ID_ERR_INT_EN | \
5105 			       B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
5106 			       B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
5107 			       B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \
5108 			       B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \
5109 			       B_BE_CT_PRE_SUB_ERR_INT_EN | \
5110 			       B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
5111 			       B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
5112 			       B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \
5113 			       B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \
5114 			       B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
5115 			       B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \
5116 			       B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
5117 			       B_BE_CR_DMA_PROCESS_ERR_INT_EN | \
5118 			       B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
5119 			       B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN)
5120 
5121 #define R_BE_RX_STOP 0x8914
5122 #define B_BE_CPU_RX_STOP BIT(17)
5123 #define B_BE_HOST_RX_STOP BIT(16)
5124 #define B_BE_CPU_RX_CH_STOP_MSK GENMASK(15, 8)
5125 #define B_BE_HOST_RX_CH_STOP_MSK GENMASK(5, 0)
5126 
5127 #define R_BE_DISP_FWD_WLAN_0 0x8938
5128 #define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30)
5129 #define B_BE_FWD_WLAN_CPU_TYPE_12_MASK GENMASK(29, 28)
5130 #define B_BE_FWD_WLAN_CPU_TYPE_11_MASK GENMASK(27, 26)
5131 #define B_BE_FWD_WLAN_CPU_TYPE_10_MASK GENMASK(25, 24)
5132 #define B_BE_FWD_WLAN_CPU_TYPE_9_MASK GENMASK(23, 22)
5133 #define B_BE_FWD_WLAN_CPU_TYPE_8_MASK GENMASK(21, 20)
5134 #define B_BE_FWD_WLAN_CPU_TYPE_7_MASK GENMASK(19, 18)
5135 #define B_BE_FWD_WLAN_CPU_TYPE_6_MASK GENMASK(17, 16)
5136 #define B_BE_FWD_WLAN_CPU_TYPE_5_MASK GENMASK(15, 14)
5137 #define B_BE_FWD_WLAN_CPU_TYPE_4_MASK GENMASK(13, 12)
5138 #define B_BE_FWD_WLAN_CPU_TYPE_3_MASK GENMASK(11, 10)
5139 #define B_BE_FWD_WLAN_CPU_TYPE_2_MASK GENMASK(9, 8)
5140 #define B_BE_FWD_WLAN_CPU_TYPE_1_MASK GENMASK(7, 6)
5141 #define B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK GENMASK(5, 4)
5142 #define B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK GENMASK(3, 2)
5143 #define B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK GENMASK(1, 0)
5144 
5145 #define R_BE_WDE_PKTBUF_CFG 0x8C08
5146 #define B_BE_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
5147 #define B_BE_WDE_START_BOUND_MASK GENMASK(14, 8)
5148 #define B_BE_WDE_PAGE_SEL_MASK GENMASK(1, 0)
5149 
5150 #define R_BE_WDE_BUFMGN_CTL 0x8C10
5151 #define B_BE_WDE_AVAL_UPD_REQ BIT(29)
5152 #define B_BE_WDE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
5153 #define B_BE_WDE_BUFMGN_FRZTMR_MODE BIT(0)
5154 
5155 #define R_BE_WDE_ERR_IMR 0x8C38
5156 #define B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
5157 #define B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
5158 #define B_BE_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
5159 #define B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
5160 #define B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
5161 #define B_BE_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
5162 #define B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(23)
5163 #define B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(22)
5164 #define B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(21)
5165 #define B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20)
5166 #define B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19)
5167 #define B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(18)
5168 #define B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(17)
5169 #define B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(16)
5170 #define B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13)
5171 #define B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12)
5172 #define B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11)
5173 #define B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10)
5174 #define B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
5175 #define B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(8)
5176 #define B_BE_WDE_GETNPG_STRPG_ERR_INT_EN BIT(7)
5177 #define B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6)
5178 #define B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(5)
5179 #define B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
5180 #define B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3)
5181 #define B_BE_WDE_BUFREQ_SIZELMT_INT_EN BIT(2)
5182 #define B_BE_WDE_BUFREQ_SIZE0_INT_EN BIT(1)
5183 #define B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
5184 #define B_BE_WDE_ERR_IMR_CLR (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \
5185 			      B_BE_WDE_BUFREQ_SIZE0_INT_EN | \
5186 			      B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \
5187 			      B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
5188 			      B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5189 			      B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \
5190 			      B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5191 			      B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \
5192 			      B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \
5193 			      B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
5194 			      B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5195 			      B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5196 			      B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5197 			      B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5198 			      B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \
5199 			      B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \
5200 			      B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \
5201 			      B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5202 			      B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5203 			      B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \
5204 			      B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \
5205 			      B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
5206 			      B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \
5207 			      B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \
5208 			      B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \
5209 			      B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \
5210 			      B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \
5211 			      B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN)
5212 #define B_BE_WDE_ERR_IMR_SET (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \
5213 			      B_BE_WDE_BUFREQ_SIZE0_INT_EN | \
5214 			      B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \
5215 			      B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
5216 			      B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5217 			      B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \
5218 			      B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5219 			      B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \
5220 			      B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \
5221 			      B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
5222 			      B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5223 			      B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5224 			      B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5225 			      B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5226 			      B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \
5227 			      B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \
5228 			      B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \
5229 			      B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5230 			      B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5231 			      B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \
5232 			      B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \
5233 			      B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
5234 			      B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \
5235 			      B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \
5236 			      B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \
5237 			      B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \
5238 			      B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \
5239 			      B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN)
5240 
5241 #define R_BE_WDE_QTA0_CFG 0x8C40
5242 #define B_BE_WDE_Q0_MAX_SIZE_MASK GENMASK(27, 16)
5243 #define B_BE_WDE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
5244 
5245 #define R_BE_WDE_QTA1_CFG 0x8C44
5246 #define B_BE_WDE_Q1_MAX_SIZE_MASK GENMASK(27, 16)
5247 #define B_BE_WDE_Q1_MIN_SIZE_MASK GENMASK(11, 0)
5248 
5249 #define R_BE_WDE_QTA2_CFG 0x8C48
5250 #define B_BE_WDE_Q2_MAX_SIZE_MASK GENMASK(27, 16)
5251 #define B_BE_WDE_Q2_MIN_SIZE_MASK GENMASK(11, 0)
5252 
5253 #define R_BE_WDE_QTA3_CFG 0x8C4C
5254 #define B_BE_WDE_Q3_MAX_SIZE_MASK GENMASK(27, 16)
5255 #define B_BE_WDE_Q3_MIN_SIZE_MASK GENMASK(11, 0)
5256 
5257 #define R_BE_WDE_QTA4_CFG 0x8C50
5258 #define B_BE_WDE_Q4_MAX_SIZE_MASK GENMASK(27, 16)
5259 #define B_BE_WDE_Q4_MIN_SIZE_MASK GENMASK(11, 0)
5260 
5261 #define R_BE_WDE_ERR1_IMR 0x8CC0
5262 #define B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN BIT(8)
5263 #define B_BE_WDE_ERR1_IMR_CLR B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN
5264 #define B_BE_WDE_ERR1_IMR_SET B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN
5265 
5266 #define R_BE_PLE_PKTBUF_CFG 0x9008
5267 #define B_BE_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
5268 #define B_BE_PLE_START_BOUND_MASK GENMASK(14, 8)
5269 #define B_BE_PLE_PAGE_SEL_MASK GENMASK(1, 0)
5270 
5271 #define R_BE_PLE_BUFMGN_CTL 0x9010
5272 #define B_BE_PLE_AVAL_UPD_REQ BIT(29)
5273 #define B_BE_PLE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
5274 #define B_BE_PLE_BUFMGN_FRZTMR_MODE BIT(0)
5275 
5276 #define R_BE_PLE_ERR_IMR 0x9038
5277 #define B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
5278 #define B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
5279 #define B_BE_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
5280 #define B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
5281 #define B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
5282 #define B_BE_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
5283 #define B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(23)
5284 #define B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(22)
5285 #define B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(21)
5286 #define B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20)
5287 #define B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19)
5288 #define B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(18)
5289 #define B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(17)
5290 #define B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(16)
5291 #define B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13)
5292 #define B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12)
5293 #define B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11)
5294 #define B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10)
5295 #define B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
5296 #define B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(8)
5297 #define B_BE_PLE_GETNPG_STRPG_ERR_INT_EN BIT(7)
5298 #define B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6)
5299 #define B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(5)
5300 #define B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4)
5301 #define B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3)
5302 #define B_BE_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
5303 #define B_BE_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
5304 #define B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
5305 #define B_BE_PLE_ERR_IMR_CLR (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \
5306 			      B_BE_PLE_BUFREQ_SIZE0_INT_EN | \
5307 			      B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \
5308 			      B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
5309 			      B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5310 			      B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \
5311 			      B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5312 			      B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \
5313 			      B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \
5314 			      B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
5315 			      B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5316 			      B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5317 			      B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5318 			      B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5319 			      B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \
5320 			      B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \
5321 			      B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \
5322 			      B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5323 			      B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5324 			      B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \
5325 			      B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \
5326 			      B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
5327 			      B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \
5328 			      B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \
5329 			      B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \
5330 			      B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \
5331 			      B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \
5332 			      B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN)
5333 #define B_BE_PLE_ERR_IMR_SET (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \
5334 			      B_BE_PLE_BUFREQ_SIZE0_INT_EN | \
5335 			      B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \
5336 			      B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
5337 			      B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
5338 			      B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \
5339 			      B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
5340 			      B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \
5341 			      B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \
5342 			      B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
5343 			      B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \
5344 			      B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \
5345 			      B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \
5346 			      B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \
5347 			      B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \
5348 			      B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \
5349 			      B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \
5350 			      B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
5351 			      B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
5352 			      B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \
5353 			      B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \
5354 			      B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
5355 			      B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \
5356 			      B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \
5357 			      B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \
5358 			      B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \
5359 			      B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \
5360 			      B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN)
5361 
5362 #define R_BE_PLE_QTA0_CFG 0x9040
5363 #define B_BE_PLE_Q0_MAX_SIZE_MASK GENMASK(27, 16)
5364 #define B_BE_PLE_Q0_MIN_SIZE_MASK GENMASK(11, 0)
5365 
5366 #define R_BE_PLE_QTA1_CFG 0x9044
5367 #define B_BE_PLE_Q1_MAX_SIZE_MASK GENMASK(27, 16)
5368 #define B_BE_PLE_Q1_MIN_SIZE_MASK GENMASK(11, 0)
5369 
5370 #define R_BE_PLE_QTA2_CFG 0x9048
5371 #define B_BE_PLE_Q2_MAX_SIZE_MASK GENMASK(27, 16)
5372 #define B_BE_PLE_Q2_MIN_SIZE_MASK GENMASK(11, 0)
5373 
5374 #define R_BE_PLE_QTA3_CFG 0x904C
5375 #define B_BE_PLE_Q3_MAX_SIZE_MASK GENMASK(27, 16)
5376 #define B_BE_PLE_Q3_MIN_SIZE_MASK GENMASK(11, 0)
5377 
5378 #define R_BE_PLE_QTA4_CFG 0x9050
5379 #define B_BE_PLE_Q4_MAX_SIZE_MASK GENMASK(27, 16)
5380 #define B_BE_PLE_Q4_MIN_SIZE_MASK GENMASK(11, 0)
5381 
5382 #define R_BE_PLE_QTA5_CFG 0x9054
5383 #define B_BE_PLE_Q5_MAX_SIZE_MASK GENMASK(27, 16)
5384 #define B_BE_PLE_Q5_MIN_SIZE_MASK GENMASK(11, 0)
5385 
5386 #define R_BE_PLE_QTA6_CFG 0x9058
5387 #define B_BE_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
5388 #define B_BE_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
5389 
5390 #define R_BE_PLE_QTA7_CFG 0x905C
5391 #define B_BE_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16)
5392 #define B_BE_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0)
5393 
5394 #define R_BE_PLE_QTA8_CFG 0x9060
5395 #define B_BE_PLE_Q8_MAX_SIZE_MASK GENMASK(27, 16)
5396 #define B_BE_PLE_Q8_MIN_SIZE_MASK GENMASK(11, 0)
5397 
5398 #define R_BE_PLE_QTA9_CFG 0x9064
5399 #define B_BE_PLE_Q9_MAX_SIZE_MASK GENMASK(27, 16)
5400 #define B_BE_PLE_Q9_MIN_SIZE_MASK GENMASK(11, 0)
5401 
5402 #define R_BE_PLE_QTA10_CFG 0x9068
5403 #define B_BE_PLE_Q10_MAX_SIZE_MASK GENMASK(27, 16)
5404 #define B_BE_PLE_Q10_MIN_SIZE_MASK GENMASK(11, 0)
5405 
5406 #define R_BE_PLE_QTA11_CFG 0x906C
5407 #define B_BE_PLE_Q11_MAX_SIZE_MASK GENMASK(27, 16)
5408 #define B_BE_PLE_Q11_MIN_SIZE_MASK GENMASK(11, 0)
5409 
5410 #define R_BE_PLE_QTA12_CFG 0x9070
5411 #define B_BE_PLE_Q12_MAX_SIZE_MASK GENMASK(27, 16)
5412 #define B_BE_PLE_Q12_MIN_SIZE_MASK GENMASK(11, 0)
5413 
5414 #define R_BE_PLE_ERRFLAG1_IMR 0x90C0
5415 #define B_BE_PLE_SRCHPG_PGOFST_IMR BIT(26)
5416 #define B_BE_PLE_SRCHPG_STRPG_IMR BIT(25)
5417 #define B_BE_PLE_SRCHPG_FRZTO_IMR BIT(24)
5418 #define B_BE_PLE_ERRFLAG1_IMR_CLR (B_BE_PLE_SRCHPG_FRZTO_IMR | \
5419 				   B_BE_PLE_SRCHPG_STRPG_IMR | \
5420 				   B_BE_PLE_SRCHPG_PGOFST_IMR)
5421 #define B_BE_PLE_ERRFLAG1_IMR_SET (B_BE_PLE_SRCHPG_FRZTO_IMR | \
5422 				   B_BE_PLE_SRCHPG_STRPG_IMR | \
5423 				   B_BE_PLE_SRCHPG_PGOFST_IMR)
5424 
5425 #define R_BE_PLE_DBG_FUN_INTF_CTL 0x9110
5426 #define B_BE_PLE_DFI_ACTIVE BIT(31)
5427 #define B_BE_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
5428 #define B_BE_PLE_DFI_ADDR_MASK GENMASK(15, 0)
5429 
5430 #define R_BE_PLE_DBG_FUN_INTF_DATA 0x9114
5431 #define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0)
5432 
5433 #define R_BE_WDRLS_CFG 0x9408
5434 #define B_BE_WDRLS_DIS_AGAC BIT(31)
5435 #define B_BE_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
5436 #define B_BE_RLSRPT_BUFREQ_TO_SEL_MASK GENMASK(7, 6)
5437 #define B_BE_WDRLS_MODE_MASK GENMASK(1, 0)
5438 
5439 #define R_BE_WDRLS_ERR_IMR 0x9430
5440 #define B_BE_WDRLS_RPT3_FRZTO_ERR_INT_EN BIT(21)
5441 #define B_BE_WDRLS_RPT3_AGGNUM0_ERR_INT_EN BIT(20)
5442 #define B_BE_WDRLS_RPT2_FRZTO_ERR_INT_EN BIT(17)
5443 #define B_BE_WDRLS_RPT2_AGGNUM0_ERR_INT_EN BIT(16)
5444 #define B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13)
5445 #define B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12)
5446 #define B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
5447 #define B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8)
5448 #define B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5)
5449 #define B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
5450 #define B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2)
5451 #define B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1)
5452 #define B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
5453 #define B_BE_WDRLS_ERR_IMR_CLR (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
5454 				B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
5455 				B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \
5456 				B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
5457 				B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
5458 				B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
5459 				B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
5460 				B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
5461 				B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN)
5462 #define B_BE_WDRLS_ERR_IMR_SET (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
5463 				B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
5464 				B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \
5465 				B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
5466 				B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
5467 				B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
5468 				B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
5469 				B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN)
5470 
5471 #define R_BE_RLSRPT0_CFG1 0x9444
5472 #define B_BE_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
5473 #define S_BE_WDRLS_FLTR_TXOK 1
5474 #define S_BE_WDRLS_FLTR_RTYLMT 2
5475 #define S_BE_WDRLS_FLTR_LIFTIM 4
5476 #define S_BE_WDRLS_FLTR_MACID 8
5477 #define B_BE_RLSRPT0_TO_MASK GENMASK(23, 16)
5478 #define B_BE_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
5479 
5480 #define R_BE_BBRPT_COM_ERR_IMR 0x9608
5481 #define B_BE_BBRPT_COM_EVT01_ISR_EN BIT(1)
5482 #define B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN BIT(0)
5483 #define B_BE_BBRPT_COM_ERR_IMR_CLR (B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN | \
5484 				    B_BE_BBRPT_COM_EVT01_ISR_EN)
5485 #define B_BE_BBRPT_COM_ERR_IMR_SET B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN
5486 
5487 #define R_BE_BBRPT_CHINFO_ERR_IMR 0x9628
5488 #define B_BE_ERR_BB_ONETEN_INT_EN BIT(1)
5489 #define B_BE_ERR_GEN_FRZTO_INT_EN BIT(0)
5490 #define B_BE_BBRPT_CHINFO_ERR_IMR_CLR (B_BE_ERR_GEN_FRZTO_INT_EN | \
5491 				       B_BE_ERR_BB_ONETEN_INT_EN)
5492 #define B_BE_BBRPT_CHINFO_ERR_IMR_SET (B_BE_ERR_GEN_FRZTO_INT_EN | \
5493 				       B_BE_ERR_BB_ONETEN_INT_EN)
5494 
5495 #define R_BE_BBRPT_DFS_ERR_IMR 0x9638
5496 #define B_BE_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
5497 #define B_BE_BBRPT_DFS_ERR_IMR_CLR B_BE_BBRPT_DFS_TO_ERR_INT_EN
5498 #define B_BE_BBRPT_DFS_ERR_IMR_SET B_BE_BBRPT_DFS_TO_ERR_INT_EN
5499 
5500 #define R_BE_LA_ERRFLAG_IMR 0x9668
5501 #define B_BE_LA_IMR_DATA_LOSS BIT(0)
5502 #define B_BE_LA_ERRFLAG_IMR_CLR B_BE_LA_IMR_DATA_LOSS
5503 #define B_BE_LA_ERRFLAG_IMR_SET B_BE_LA_IMR_DATA_LOSS
5504 
5505 #define R_BE_LA_ERRFLAG_ISR 0x966C
5506 #define B_BE_LA_ISR_DATA_LOSS BIT(0)
5507 
5508 #define R_BE_CH_INFO_DBGFLAG_IMR 0x9688
5509 #define B_BE_BCHN_EVT01_ISR_EN BIT(29)
5510 #define B_BE_BCHN_REQTO_ISR_EN BIT(28)
5511 #define B_BE_CHIF_RXDATA_AFACT_ISR_EN BIT(11)
5512 #define B_BE_CHIF_RXDATA_BFACT_ISR_EN BIT(10)
5513 #define B_BE_CHIF_HDR_SEGLEN_ISR_EN BIT(9)
5514 #define B_BE_CHIF_HDR_INVLD_ISR_EN BIT(8)
5515 #define B_BE_CHIF_BBONL_BFACT_ISR_EN BIT(4)
5516 #define B_BE_CHIF_RPT_OVF_ISR_EN BIT(3)
5517 #define B_BE_DBG_CHIF_DATA_LOSS_ISR_EN BIT(2)
5518 #define B_BE_CHIF_DATA_WTOUT_ISR_EN BIT(1)
5519 #define B_BE_CHIF_RPT_WTOUT_ISR_EN BIT(0)
5520 #define B_BE_CH_INFO_DBGFLAG_IMR_CLR (B_BE_CHIF_RPT_WTOUT_ISR_EN | \
5521 				      B_BE_CHIF_DATA_WTOUT_ISR_EN | \
5522 				      B_BE_DBG_CHIF_DATA_LOSS_ISR_EN | \
5523 				      B_BE_CHIF_RPT_OVF_ISR_EN | \
5524 				      B_BE_CHIF_HDR_INVLD_ISR_EN | \
5525 				      B_BE_CHIF_HDR_SEGLEN_ISR_EN | \
5526 				      B_BE_CHIF_RXDATA_BFACT_ISR_EN | \
5527 				      B_BE_CHIF_RXDATA_AFACT_ISR_EN)
5528 #define B_BE_CH_INFO_DBGFLAG_IMR_SET 0
5529 
5530 #define R_BE_WD_BUF_REQ 0x9800
5531 #define B_BE_WD_BUF_REQ_EXEC BIT(31)
5532 #define B_BE_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
5533 #define B_BE_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
5534 
5535 #define R_BE_WD_BUF_STATUS 0x9804
5536 #define B_BE_WD_BUF_STAT_DONE BIT(31)
5537 #define B_BE_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
5538 
5539 #define R_BE_WD_CPUQ_OP_0 0x9810
5540 #define B_BE_WD_CPUQ_OP_EXEC BIT(31)
5541 #define B_BE_WD_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
5542 #define B_BE_WD_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5543 
5544 #define R_BE_WD_CPUQ_OP_1 0x9814
5545 #define B_BE_WD_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12)
5546 #define B_BE_WD_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5547 #define B_BE_WD_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)
5548 
5549 #define R_BE_WD_CPUQ_OP_2 0x9818
5550 #define B_BE_WD_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12)
5551 #define B_BE_WD_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5552 #define B_BE_WD_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)
5553 
5554 #define R_BE_WD_CPUQ_OP_3 0x981C
5555 #define B_BE_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
5556 #define B_BE_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
5557 
5558 #define R_BE_WD_CPUQ_OP_STATUS 0x9820
5559 #define B_BE_WD_CPUQ_OP_STAT_DONE BIT(31)
5560 #define B_BE_WD_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16)
5561 #define B_BE_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
5562 
5563 #define R_BE_PL_BUF_REQ 0x9840
5564 #define B_BE_PL_BUF_REQ_EXEC BIT(31)
5565 #define B_BE_PL_BUF_REQ_QUOTA_ID_MASK GENMASK(19, 16)
5566 #define B_BE_PL_BUF_REQ_LEN_MASK GENMASK(15, 0)
5567 
5568 #define R_BE_PL_BUF_STATUS 0x9844
5569 #define B_BE_PL_BUF_STAT_DONE BIT(31)
5570 #define B_BE_PL_BUF_STAT_PKTID_MASK GENMASK(11, 0)
5571 
5572 #define R_BE_PL_CPUQ_OP_0 0x9850
5573 #define B_BE_PL_CPUQ_OP_EXEC BIT(31)
5574 #define B_BE_PL_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
5575 #define B_BE_PL_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
5576 
5577 #define R_BE_PL_CPUQ_OP_1 0x9854
5578 #define B_BE_PL_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12)
5579 #define B_BE_PL_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5580 #define B_BE_PL_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0)
5581 
5582 #define R_BE_PL_CPUQ_OP_2 0x9858
5583 #define B_BE_PL_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12)
5584 #define B_BE_PL_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5585 #define B_BE_PL_CPUQ_OP_DST_PID_MASK GENMASK(2, 0)
5586 
5587 #define R_BE_PL_CPUQ_OP_3 0x985C
5588 #define B_BE_PL_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
5589 #define B_BE_PL_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
5590 
5591 #define R_BE_PL_CPUQ_OP_STATUS 0x9860
5592 #define B_BE_PL_CPUQ_OP_STAT_DONE BIT(31)
5593 #define B_BE_PL_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16)
5594 #define B_BE_PL_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
5595 
5596 #define R_BE_CPUIO_ERR_IMR 0x9888
5597 #define B_BE_PLEQUE_OP_ERR_INT_EN BIT(12)
5598 #define B_BE_PLEBUF_OP_ERR_INT_EN BIT(8)
5599 #define B_BE_WDEQUE_OP_ERR_INT_EN BIT(4)
5600 #define B_BE_WDEBUF_OP_ERR_INT_EN BIT(0)
5601 #define B_BE_CPUIO_ERR_IMR_CLR (B_BE_WDEBUF_OP_ERR_INT_EN | \
5602 				B_BE_WDEQUE_OP_ERR_INT_EN | \
5603 				B_BE_PLEBUF_OP_ERR_INT_EN | \
5604 				B_BE_PLEQUE_OP_ERR_INT_EN)
5605 #define B_BE_CPUIO_ERR_IMR_SET (B_BE_WDEBUF_OP_ERR_INT_EN | \
5606 				B_BE_WDEQUE_OP_ERR_INT_EN | \
5607 				B_BE_PLEBUF_OP_ERR_INT_EN | \
5608 				B_BE_PLEQUE_OP_ERR_INT_EN)
5609 
5610 #define R_BE_PKTIN_ERR_IMR 0x9A20
5611 #define B_BE_SW_MERGE_ERR_INT_EN BIT(1)
5612 #define B_BE_GET_NULL_PKTID_ERR_INT_EN BIT(0)
5613 #define B_BE_PKTIN_ERR_IMR_CLR (B_BE_SW_MERGE_ERR_INT_EN | \
5614 				B_BE_GET_NULL_PKTID_ERR_INT_EN)
5615 #define B_BE_PKTIN_ERR_IMR_SET (B_BE_SW_MERGE_ERR_INT_EN | \
5616 				B_BE_GET_NULL_PKTID_ERR_INT_EN)
5617 
5618 #define R_BE_HDR_SHCUT_SETTING 0x9B00
5619 #define B_BE_TX_ADDR_MLD_TO_LIK BIT(4)
5620 #define B_BE_TX_HW_SEC_HDR_EN BIT(3)
5621 #define B_BE_TX_MAC_MPDU_PROC_EN BIT(2)
5622 #define B_BE_TX_HW_ACK_POLICY_EN BIT(1)
5623 #define B_BE_TX_HW_SEQ_EN BIT(0)
5624 
5625 #define R_BE_MPDU_TX_ERR_IMR 0x9BF4
5626 #define B_BE_TX_TIMEOUT_ERR_EN BIT(0)
5627 #define B_BE_MPDU_TX_ERR_IMR_CLR B_BE_TX_TIMEOUT_ERR_EN
5628 #define B_BE_MPDU_TX_ERR_IMR_SET 0
5629 
5630 #define R_BE_MPDU_PROC 0x9C00
5631 #define B_BE_PORT_SEL BIT(29)
5632 #define B_BE_WPKT_WLANCPU_QSEL_MASK GENMASK(28, 27)
5633 #define B_BE_WPKT_DATACPU_QSEL_MASK GENMASK(26, 25)
5634 #define B_BE_WPKT_FW_RLS BIT(24)
5635 #define B_BE_FWD_RPKT_MASK GENMASK(23, 16)
5636 #define B_BE_FWD_WPKT_MASK GENMASK(15, 8)
5637 #define B_BE_RXFWD_PRIO_MASK GENMASK(5, 4)
5638 #define B_BE_RXFWD_EN BIT(3)
5639 #define B_BE_DROP_NONDMA_PPDU BIT(2)
5640 #define B_BE_APPEND_FCS BIT(0)
5641 
5642 #define R_BE_FWD_ERR 0x9C10
5643 #define R_BE_FWD_ACTN0 0x9C14
5644 #define R_BE_FWD_ACTN1 0x9C18
5645 #define R_BE_FWD_ACTN2 0x9C1C
5646 #define R_BE_FWD_TF0 0x9C20
5647 #define R_BE_FWD_TF1 0x9C24
5648 
5649 #define R_BE_HW_PPDU_STATUS 0x9C30
5650 #define B_BE_FWD_RPKTTYPE_MASK GENMASK(31, 26)
5651 #define B_BE_FWD_PPDU_PRTID_MASK GENMASK(25, 23)
5652 #define B_BE_FWD_PPDU_FW_RLS BIT(22)
5653 #define B_BE_FWD_PPDU_QUEID_MASK GENMASK(21, 16)
5654 #define B_BE_FWD_OTHER_RPKT_MASK GENMASK(15, 8)
5655 #define B_BE_FWD_PPDU_STAT_MASK GENMASK(7, 0)
5656 
5657 #define R_BE_CUT_AMSDU_CTRL 0x9C94
5658 #define B_BE_EN_CUT_AMSDU BIT(31)
5659 #define B_BE_CUT_AMSDU_CHKLEN_EN BIT(30)
5660 #define B_BE_CA_CHK_ADDRCAM_EN BIT(29)
5661 #define B_BE_MPDU_CUT_CTRL_EN BIT(24)
5662 #define B_BE_CUT_AMSDU_CHKLEN_L_TH_MASK GENMASK(23, 16)
5663 #define B_BE_CUT_AMSDU_CHKLEN_H_TH_MASK GENMASK(15, 0)
5664 
5665 #define R_BE_WOW_CTRL 0x9CB8
5666 #define B_BE_WOW_HCI BIT(5)
5667 #define B_BE_WOW_DROP BIT(2)
5668 #define B_BE_WOW_WOWEN BIT(1)
5669 #define B_BE_WOW_FORCE_WAKEUP BIT(0)
5670 
5671 #define R_BE_RX_HDRTRNS 0x9CC0
5672 #define B_BE_RX_MGN_MLD_ADDR_EN BIT(6)
5673 #define B_BE_HDR_INFO_MASK GENMASK(5, 4)
5674 #define B_BE_HC_ADDR_HIT_EN BIT(3)
5675 #define B_BE_RX_ADDR_LINK_TO_MLO BIT(2)
5676 #define B_BE_HDR_CNV BIT(1)
5677 #define B_BE_RX_HDR_CNV_EN BIT(0)
5678 #define TRXCFG_MPDU_PROC_RX_HDR_CONV	0x00000000
5679 
5680 #define R_BE_MPDU_RX_ERR_IMR 0x9CF4
5681 #define B_BE_LEN_ERR_IMR BIT(3)
5682 #define B_BE_TIMEOUT_ERR_IMR BIT(1)
5683 #define B_BE_MPDU_RX_ERR_IMR_CLR B_BE_TIMEOUT_ERR_IMR
5684 #define B_BE_MPDU_RX_ERR_IMR_SET 0
5685 
5686 #define R_BE_SEC_ENG_CTRL 0x9D00
5687 #define B_BE_SEC_ENG_EN BIT(31)
5688 #define B_BE_CCMP_SPP_MIC BIT(30)
5689 #define B_BE_CCMP_SPP_CTR BIT(29)
5690 #define B_BE_SEC_CAM_ACC BIT(28)
5691 #define B_BE_WMAC_SEC_PN_SEL_MASK GENMASK(27, 26)
5692 #define B_BE_WMAC_SEC_MASKIV BIT(25)
5693 #define B_BE_WAPI_SPEC BIT(24)
5694 #define B_BE_REVERT_TA_RA_MLD_EN BIT(23)
5695 #define B_BE_SEC_DBG_SEL_MASK GENMASK(19, 16)
5696 #define B_BE_CAM_FORCE_CLK BIT(15)
5697 #define B_BE_SEC_FORCE_CLK BIT(14)
5698 #define B_BE_SEC_RX_SHORT_ADD_ICVERR BIT(13)
5699 #define B_BE_SRAM_IO_PROT BIT(12)
5700 #define B_BE_SEC_PRE_ENQUE_TX BIT(11)
5701 #define B_BE_CLK_EN_CGCMP BIT(10)
5702 #define B_BE_CLK_EN_WAPI BIT(9)
5703 #define B_BE_CLK_EN_WEP_TKIP BIT(8)
5704 #define B_BE_BMC_MGNT_DEC BIT(5)
5705 #define B_BE_UC_MGNT_DEC BIT(4)
5706 #define B_BE_MC_DEC BIT(3)
5707 #define B_BE_BC_DEC BIT(2)
5708 #define B_BE_SEC_RX_DEC BIT(1)
5709 #define B_BE_SEC_TX_ENC BIT(0)
5710 
5711 #define R_BE_SEC_MPDU_PROC 0x9D04
5712 #define B_BE_DBG_ENGINE_SEL BIT(8)
5713 #define B_BE_STOP_RX_PKT_HANDLE BIT(7)
5714 #define B_BE_STOP_TX_PKT_HANDLE BIT(6)
5715 #define B_BE_QUEUE_FOWARD_SEL BIT(5)
5716 #define B_BE_RESP1_PROTECT BIT(4)
5717 #define B_BE_RESP0_PROTECT BIT(3)
5718 #define B_BE_TX_ACTIVE_PROTECT BIT(2)
5719 #define B_BE_APPEND_ICV BIT(1)
5720 #define B_BE_APPEND_MIC BIT(0)
5721 
5722 #define R_BE_SEC_CAM_ACCESS 0x9D10
5723 #define B_BE_SEC_TIME_OUT_MASK GENMASK(31, 16)
5724 #define B_BE_SEC_CAM_POLL BIT(15)
5725 #define B_BE_SEC_CAM_RW BIT(14)
5726 #define B_BE_SEC_CAM_ACC_FAIL BIT(13)
5727 #define B_BE_SEC_CAM_OFFSET_MASK GENMASK(10, 0)
5728 
5729 #define R_BE_SEC_CAM_RDATA 0x9D14
5730 #define B_BE_SEC_CAM_RDATA_MASK GENMASK(31, 0)
5731 
5732 #define R_BE_SEC_DEBUG2 0x9D28
5733 #define B_BE_DBG_READ_MASK GENMASK(31, 0)
5734 
5735 #define R_BE_SEC_ERROR_IMR 0x9D2C
5736 #define B_BE_QUEUE_OPERATION_HANG_IMR BIT(4)
5737 #define B_BE_SEC1_RX_HANG_IMR BIT(3)
5738 #define B_BE_SEC1_TX_HANG_IMR BIT(2)
5739 #define B_BE_RX_HANG_IMR BIT(1)
5740 #define B_BE_TX_HANG_IMR BIT(0)
5741 #define B_BE_SEC_ERROR_IMR_CLR (B_BE_TX_HANG_IMR | \
5742 				B_BE_RX_HANG_IMR | \
5743 				B_BE_SEC1_TX_HANG_IMR | \
5744 				B_BE_SEC1_RX_HANG_IMR | \
5745 				B_BE_QUEUE_OPERATION_HANG_IMR)
5746 #define B_BE_SEC_ERROR_IMR_SET (B_BE_TX_HANG_IMR | \
5747 				B_BE_RX_HANG_IMR | \
5748 				B_BE_SEC1_TX_HANG_IMR | \
5749 				B_BE_SEC1_RX_HANG_IMR | \
5750 				B_BE_QUEUE_OPERATION_HANG_IMR)
5751 
5752 #define R_BE_SEC_ERROR_FLAG 0x9D30
5753 #define B_BE_TXD_DIFF_KEYCAM_TYPE_ERROR BIT(5)
5754 #define B_BE_QUEUE_OPERATION_HANG_ERROR BIT(4)
5755 #define B_BE_SEC1_RX_HANG_ERROR BIT(3)
5756 #define B_BE_SEC1_TX_HANG_ERROR BIT(2)
5757 #define B_BE_RX_HANG_ERROR BIT(1)
5758 #define B_BE_TX_HANG_ERROR BIT(0)
5759 
5760 #define R_BE_TXPKTCTL_MPDUINFO_CFG 0x9F10
5761 #define B_BE_MPDUINFO_FEN BIT(31)
5762 #define B_BE_MPDUINFO_PKTID_MASK GENMASK(27, 16)
5763 #define B_BE_MPDUINFO_B1_BADDR_MASK GENMASK(5, 0)
5764 #define MPDU_INFO_B1_OFST 18
5765 
5766 #define R_BE_TXPKTCTL_B0_PRELD_CFG0 0x9F48
5767 #define B_BE_B0_PRELD_FEN BIT(31)
5768 #define B_BE_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
5769 #define B_BE_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
5770 #define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5771 
5772 #define R_BE_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
5773 #define B_BE_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
5774 #define B_BE_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5775 
5776 #define R_BE_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
5777 #define B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN BIT(25)
5778 #define B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
5779 #define B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(17)
5780 #define B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(16)
5781 #define B_BE_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11)
5782 #define B_BE_B0_IMR_ERR_CMDPSR_FRZTO BIT(10)
5783 #define B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
5784 #define B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
5785 #define B_BE_B0_IMR_ERR_USRCTL_NOINIT BIT(1)
5786 #define B_BE_B0_IMR_ERR_USRCTL_REINIT BIT(0)
5787 #define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR (B_BE_B0_IMR_ERR_USRCTL_REINIT | \
5788 					  B_BE_B0_IMR_ERR_USRCTL_NOINIT | \
5789 					  B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD | \
5790 					  B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN | \
5791 					  B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \
5792 					  B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \
5793 					  B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \
5794 					  B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \
5795 					  B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
5796 					  B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG)
5797 #define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET (B_BE_B0_IMR_ERR_USRCTL_REINIT | \
5798 					  B_BE_B0_IMR_ERR_USRCTL_NOINIT | \
5799 					  B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \
5800 					  B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \
5801 					  B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \
5802 					  B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \
5803 					  B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
5804 					  B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG)
5805 
5806 #define R_BE_TXPKTCTL_B1_PRELD_CFG0 0x9F88
5807 #define B_BE_B1_PRELD_FEN BIT(31)
5808 #define B_BE_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
5809 #define B_BE_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
5810 #define B_BE_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5811 
5812 #define R_BE_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
5813 #define B_BE_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
5814 #define B_BE_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
5815 
5816 #define R_BE_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
5817 #define B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN BIT(25)
5818 #define B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
5819 #define B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(17)
5820 #define B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(16)
5821 #define B_BE_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11)
5822 #define B_BE_B1_IMR_ERR_CMDPSR_FRZTO BIT(10)
5823 #define B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
5824 #define B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
5825 #define B_BE_B1_IMR_ERR_USRCTL_NOINIT BIT(1)
5826 #define B_BE_B1_IMR_ERR_USRCTL_REINIT BIT(0)
5827 #define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR (B_BE_B1_IMR_ERR_USRCTL_REINIT | \
5828 					  B_BE_B1_IMR_ERR_USRCTL_NOINIT | \
5829 					  B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD | \
5830 					  B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN | \
5831 					  B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \
5832 					  B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \
5833 					  B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \
5834 					  B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \
5835 					  B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
5836 					  B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG)
5837 #define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET (B_BE_B1_IMR_ERR_USRCTL_REINIT | \
5838 					  B_BE_B1_IMR_ERR_USRCTL_NOINIT | \
5839 					  B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \
5840 					  B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \
5841 					  B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \
5842 					  B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \
5843 					  B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
5844 					  B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG)
5845 
5846 #define R_BE_MLO_INIT_CTL 0xA114
5847 #define B_BE_MLO_TABLE_INIT_DONE BIT(31)
5848 #define B_BE_MLO_TABLE_CLR_DONE BIT(30)
5849 #define B_BE_MLO_TABLE_REINIT BIT(23)
5850 #define B_BE_MLO_TABLE_HW_FLAG_CLR BIT(22)
5851 
5852 #define R_BE_MLO_ERR_IDCT_IMR 0xA128
5853 #define B_BE_MLO_ERR_IDCT_IMR_0 BIT(31)
5854 #define B_BE_MLO_ERR_IDCT_IMR_1 BIT(30)
5855 #define B_BE_MLO_ERR_IDCT_IMR_2 BIT(29)
5856 #define B_BE_MLO_ERR_IDCT_IMR_3 BIT(28)
5857 #define B_BE_MLO_ERR_IDCT_IMR_CLR (B_BE_MLO_ERR_IDCT_IMR_2 | \
5858 				   B_BE_MLO_ERR_IDCT_IMR_1 | \
5859 				   B_BE_MLO_ERR_IDCT_IMR_0)
5860 #define B_BE_MLO_ERR_IDCT_IMR_SET (B_BE_MLO_ERR_IDCT_IMR_2 | \
5861 				   B_BE_MLO_ERR_IDCT_IMR_1 | \
5862 				   B_BE_MLO_ERR_IDCT_IMR_0)
5863 
5864 #define R_BE_MLO_ERR_IDCT_ISR 0xA12C
5865 #define B_BE_MLO_ISR_IDCT_0 BIT(31)
5866 #define B_BE_MLO_ISR_IDCT_1 BIT(30)
5867 #define B_BE_MLO_ISR_IDCT_2 BIT(29)
5868 #define B_BE_MLO_ISR_IDCT_3 BIT(28)
5869 
5870 #define R_BE_PLRLS_ERR_IMR 0xA218
5871 #define B_BE_PLRLS_CTL_FRZTO_IMR BIT(0)
5872 #define B_BE_PLRLS_ERR_IMR_CLR B_BE_PLRLS_CTL_FRZTO_IMR
5873 #define B_BE_PLRLS_ERR_IMR_SET B_BE_PLRLS_CTL_FRZTO_IMR
5874 
5875 #define R_BE_PLRLS_ERR_ISR 0xA21C
5876 #define B_BE_PLRLS_CTL_EVT03_ISR BIT(3)
5877 #define B_BE_PLRLS_CTL_EVT02_ISR BIT(2)
5878 #define B_BE_PLRLS_CTL_EVT01_ISR BIT(1)
5879 #define B_BE_PLRLS_CTL_FRZTO_ISR BIT(0)
5880 
5881 #define R_BE_SS_CTRL 0xA310
5882 #define B_BE_SS_INIT_DONE BIT(31)
5883 #define B_BE_WDE_STA_DIS BIT(30)
5884 #define B_BE_WARM_INIT BIT(29)
5885 #define B_BE_BAND_TRIG_EN BIT(28)
5886 #define B_BE_RMAC_REQ_DIS BIT(27)
5887 #define B_BE_DLYTX_SEL_MASK GENMASK(25, 24)
5888 #define B_BE_WMM3_SWITCH_MASK GENMASK(23, 22)
5889 #define B_BE_WMM2_SWITCH_MASK GENMASK(21, 20)
5890 #define B_BE_WMM1_SWITCH_MASK GENMASK(19, 18)
5891 #define B_BE_WMM0_SWITCH_MASK GENMASK(17, 16)
5892 #define B_BE_STA_OPTION_CR BIT(15)
5893 #define B_BE_EMLSR_STA_EMPTY_EN BIT(11)
5894 #define B_BE_MLO_HW_CHGLINK_EN BIT(10)
5895 #define B_BE_BAND1_TRIG_EN BIT(9)
5896 #define B_BE_RMAC1_REQ_DIS BIT(8)
5897 #define B_BE_MRT_SRAM_EN BIT(7)
5898 #define B_BE_MRT_INIT_EN BIT(6)
5899 #define B_BE_AVG_LENG_EN BIT(5)
5900 #define B_BE_AVG_INIT_EN BIT(4)
5901 #define B_BE_LENG_INIT_EN BIT(2)
5902 #define B_BE_PMPA_INIT_EN BIT(1)
5903 #define B_BE_SS_EN BIT(0)
5904 
5905 #define R_BE_INTERRUPT_MASK_REG 0xA3F0
5906 #define B_BE_PLE_B_PKTID_ERR_IMR BIT(2)
5907 #define B_BE_RPT_TIMEOUT_IMR BIT(1)
5908 #define B_BE_SEARCH_TIMEOUT_IMR BIT(0)
5909 #define B_BE_INTERRUPT_MASK_REG_CLR (B_BE_SEARCH_TIMEOUT_IMR | \
5910 				     B_BE_RPT_TIMEOUT_IMR | \
5911 				     B_BE_PLE_B_PKTID_ERR_IMR)
5912 #define B_BE_INTERRUPT_MASK_REG_SET (B_BE_SEARCH_TIMEOUT_IMR | \
5913 				     B_BE_RPT_TIMEOUT_IMR | \
5914 				     B_BE_PLE_B_PKTID_ERR_IMR)
5915 
5916 #define R_BE_INTERRUPT_STS_REG 0xA3F4
5917 #define B_BE_PLE_B_PKTID_ERR_ISR BIT(2)
5918 #define B_BE_RPT_TIMEOUT_ISR BIT(1)
5919 #define B_BE_SEARCH_TIMEOUT_ISR BIT(0)
5920 
5921 #define R_BE_HAXI_INIT_CFG1 0xB000
5922 #define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28)
5923 #define B_BE_CFG_WD_PERIOD_ACTIVE_MASK GENMASK(27, 24)
5924 #define B_BE_EN_RO_IDX_UPD_BY_IO BIT(19)
5925 #define B_BE_RST_KEEP_REG BIT(18)
5926 #define B_BE_FLUSH_HAXI_MST BIT(17)
5927 #define B_BE_SET_BDRAM_BOUND BIT(16)
5928 #define B_BE_ADDRINFO_ALIGN4B_EN BIT(15)
5929 #define B_BE_RXBD_DONE_MODE_MASK GENMASK(14, 13)
5930 #define B_BE_RXQ_RXBD_MODE_MASK GENMASK(12, 11)
5931 #define B_BE_DMA_MODE_MASK GENMASK(10, 8)
5932 #define S_BE_DMA_MOD_PCIE_NO_DATA_CPU 0x0
5933 #define S_BE_DMA_MOD_PCIE_DATA_CPU 0x1
5934 #define S_BE_DMA_MOD_USB 0x4
5935 #define S_BE_DMA_MOD_SDIO 0x6
5936 #define B_BE_STOP_AXI_MST BIT(7)
5937 #define B_BE_RXDMA_ALIGN64B_EN BIT(6)
5938 #define B_BE_RXDMA_EN BIT(5)
5939 #define B_BE_TXDMA_EN BIT(4)
5940 #define B_BE_MAX_RXDMA_MASK GENMASK(3, 2)
5941 #define B_BE_MAX_TXDMA_MASK GENMASK(1, 0)
5942 
5943 #define R_BE_HAXI_DMA_STOP1 0xB010
5944 #define B_BE_STOP_WPDMA BIT(31)
5945 #define B_BE_STOP_CH14 BIT(14)
5946 #define B_BE_STOP_CH13 BIT(13)
5947 #define B_BE_STOP_CH12 BIT(12)
5948 #define B_BE_STOP_CH11 BIT(11)
5949 #define B_BE_STOP_CH10 BIT(10)
5950 #define B_BE_STOP_CH9 BIT(9)
5951 #define B_BE_STOP_CH8 BIT(8)
5952 #define B_BE_STOP_CH7 BIT(7)
5953 #define B_BE_STOP_CH6 BIT(6)
5954 #define B_BE_STOP_CH5 BIT(5)
5955 #define B_BE_STOP_CH4 BIT(4)
5956 #define B_BE_STOP_CH3 BIT(3)
5957 #define B_BE_STOP_CH2 BIT(2)
5958 #define B_BE_STOP_CH1 BIT(1)
5959 #define B_BE_STOP_CH0 BIT(0)
5960 
5961 #define R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1 0xB02C
5962 #define B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK GENMASK(4, 0)
5963 
5964 #define R_BE_HAXI_IDCT_MSK 0xB0B8
5965 #define B_BE_HAXI_RRESP_ERR_IDCT_MSK BIT(7)
5966 #define B_BE_HAXI_BRESP_ERR_IDCT_MSK BIT(6)
5967 #define B_BE_RXDMA_ERR_FLAG_IDCT_MSK BIT(5)
5968 #define B_BE_SET_FC_ERROR_FLAG_IDCT_MSK BIT(4)
5969 #define B_BE_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
5970 #define B_BE_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
5971 #define B_BE_RXMDA_STUCK_IDCT_MSK BIT(1)
5972 #define B_BE_TXMDA_STUCK_IDCT_MSK BIT(0)
5973 #define B_BE_HAXI_IDCT_MSK_CLR (B_BE_TXMDA_STUCK_IDCT_MSK | \
5974 				B_BE_RXMDA_STUCK_IDCT_MSK | \
5975 				B_BE_TXBD_LEN0_ERR_IDCT_MSK | \
5976 				B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \
5977 				B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \
5978 				B_BE_HAXI_BRESP_ERR_IDCT_MSK | \
5979 				B_BE_HAXI_RRESP_ERR_IDCT_MSK)
5980 #define B_BE_HAXI_IDCT_MSK_SET (B_BE_TXMDA_STUCK_IDCT_MSK | \
5981 				B_BE_RXMDA_STUCK_IDCT_MSK | \
5982 				B_BE_TXBD_LEN0_ERR_IDCT_MSK | \
5983 				B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \
5984 				B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \
5985 				B_BE_HAXI_BRESP_ERR_IDCT_MSK | \
5986 				B_BE_HAXI_RRESP_ERR_IDCT_MSK)
5987 
5988 #define R_BE_HAXI_IDCT 0xB0BC
5989 #define B_BE_HAXI_RRESP_ERR_IDCT BIT(7)
5990 #define B_BE_HAXI_BRESP_ERR_IDCT BIT(6)
5991 #define B_BE_RXDMA_ERR_FLAG_IDCT BIT(5)
5992 #define B_BE_SET_FC_ERROR_FLAG_IDCT BIT(4)
5993 #define B_BE__TXBD_LEN0_ERR_IDCT BIT(3)
5994 #define B_BE__TXBD_4KBOUND_ERR_IDCT BIT(2)
5995 #define B_BE_RXMDA_STUCK_IDCT BIT(1)
5996 #define B_BE_TXMDA_STUCK_IDCT BIT(0)
5997 
5998 #define R_BE_HCI_FC_CTRL 0xB700
5999 #define B_BE_WD_PAGE_MODE_MASK GENMASK(17, 16)
6000 #define B_BE_HCI_FC_CH14_FULL_COND_MASK GENMASK(15, 14)
6001 #define B_BE_HCI_FC_TWD_FULL_COND_MASK GENMASK(13, 12)
6002 #define B_BE_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
6003 #define B_BE_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
6004 #define B_BE_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
6005 #define B_BE_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
6006 #define B_BE_HCI_FC_CH12_EN BIT(3)
6007 #define B_BE_HCI_FC_MODE_MASK GENMASK(2, 1)
6008 #define B_BE_HCI_FC_EN BIT(0)
6009 
6010 #define R_BE_CH_PAGE_CTRL 0xB704
6011 #define B_BE_PREC_PAGE_CH12_V1_MASK GENMASK(21, 16)
6012 #define B_BE_PREC_PAGE_CH011_V1_MASK GENMASK(5, 0)
6013 
6014 #define R_BE_CH0_PAGE_CTRL 0xB718
6015 #define B_BE_CH0_GRP BIT(31)
6016 #define B_BE_CH0_MAX_PG_MASK GENMASK(28, 16)
6017 #define B_BE_CH0_MIN_PG_MASK GENMASK(12, 0)
6018 
6019 #define R_BE_CH0_PAGE_INFO 0xB750
6020 #define B_BE_CH0_AVAL_PG_MASK GENMASK(28, 16)
6021 #define B_BE_CH0_USE_PG_MASK GENMASK(12, 0)
6022 
6023 #define R_BE_PUB_PAGE_INFO3 0xB78C
6024 #define B_BE_G1_AVAL_PG_MASK GENMASK(28, 16)
6025 #define B_BE_G0_AVAL_PG_MASK GENMASK(12, 0)
6026 
6027 #define R_BE_PUB_PAGE_CTRL1 0xB790
6028 #define B_BE_PUBPG_G1_MASK GENMASK(28, 16)
6029 #define B_BE_PUBPG_G0_MASK GENMASK(12, 0)
6030 
6031 #define R_BE_PUB_PAGE_CTRL2 0xB794
6032 #define B_BE_PUBPG_ALL_MASK GENMASK(12, 0)
6033 
6034 #define R_BE_PUB_PAGE_INFO1 0xB79C
6035 #define B_BE_G1_USE_PG_MASK GENMASK(28, 16)
6036 #define B_BE_G0_USE_PG_MASK GENMASK(12, 0)
6037 
6038 #define R_BE_PUB_PAGE_INFO2 0xB7A0
6039 #define B_BE_PUB_AVAL_PG_MASK GENMASK(12, 0)
6040 
6041 #define R_BE_WP_PAGE_CTRL1 0xB7A4
6042 #define B_BE_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
6043 #define B_BE_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
6044 
6045 #define R_BE_WP_PAGE_CTRL2 0xB7A8
6046 #define B_BE_WP_THRD_MASK GENMASK(12, 0)
6047 
6048 #define R_BE_WP_PAGE_INFO1 0xB7AC
6049 #define B_BE_WP_AVAL_PG_MASK GENMASK(28, 16)
6050 
6051 #define R_BE_LTPC_T0_PATH0 0xBA28
6052 #define R_BE_LTPC_T0_PATH1 0xBB28
6053 
6054 #define R_BE_CMAC_SHARE_FUNC_EN 0x0E000
6055 #define B_BE_CMAC_SHARE_CRPRT BIT(31)
6056 #define B_BE_CMAC_SHARE_EN BIT(30)
6057 #define B_BE_FORCE_BTCOEX_REG_GCKEN BIT(24)
6058 #define B_BE_FORCE_CMAC_SHARE_COMMON_REG_GCKEN BIT(16)
6059 #define B_BE_FORCE_CMAC_SHARE_REG_GCKEN BIT(15)
6060 #define B_BE_RESPBA_EN BIT(2)
6061 #define B_BE_ADDRSRCH_EN BIT(1)
6062 #define B_BE_BTCOEX_EN BIT(0)
6063 
6064 #define R_BE_CMAC_SHARE_ACQCHK_CFG_0 0x0E010
6065 #define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24)
6066 #define B_BE_R_ACQCHK_ENTRY_IDX_SEL_MASK GENMASK(7, 4)
6067 #define B_BE_MACID_ACQ_GRP1_CLR_P BIT(3)
6068 #define B_BE_MACID_ACQ_GRP0_CLR_P BIT(2)
6069 #define B_BE_R_MACID_ACQ_CHK_EN BIT(0)
6070 
6071 #define R_BE_BT_BREAK_TABLE 0x0E344
6072 
6073 #define R_BE_GNT_SW_CTRL 0x0E348
6074 #define B_BE_WL_ACT2_VAL BIT(25)
6075 #define B_BE_WL_ACT2_SWCTRL BIT(24)
6076 #define B_BE_WL_ACT_VAL BIT(23)
6077 #define B_BE_WL_ACT_SWCTRL BIT(22)
6078 #define B_BE_GNT_BT_RX_BB1_VAL BIT(21)
6079 #define B_BE_GNT_BT_RX_BB1_SWCTRL BIT(20)
6080 #define B_BE_GNT_BT_TX_BB1_VAL BIT(19)
6081 #define B_BE_GNT_BT_TX_BB1_SWCTRL BIT(18)
6082 #define B_BE_GNT_BT_RX_BB0_VAL BIT(17)
6083 #define B_BE_GNT_BT_RX_BB0_SWCTRL BIT(16)
6084 #define B_BE_GNT_BT_TX_BB0_VAL BIT(15)
6085 #define B_BE_GNT_BT_TX_BB0_SWCTRL BIT(14)
6086 #define B_BE_GNT_WL_RX_VAL BIT(13)
6087 #define B_BE_GNT_WL_RX_SWCTRL BIT(12)
6088 #define B_BE_GNT_WL_TX_VAL BIT(11)
6089 #define B_BE_GNT_WL_TX_SWCTRL BIT(10)
6090 #define B_BE_GNT_BT_BB1_VAL BIT(9)
6091 #define B_BE_GNT_BT_BB1_SWCTRL BIT(8)
6092 #define B_BE_GNT_WL_BB1_VAL BIT(7)
6093 #define B_BE_GNT_WL_BB1_SWCTRL BIT(6)
6094 #define B_BE_GNT_BT_BB0_VAL BIT(5)
6095 #define B_BE_GNT_BT_BB0_SWCTRL BIT(4)
6096 #define B_BE_GNT_WL_BB0_VAL BIT(3)
6097 #define B_BE_GNT_WL_BB0_SWCTRL BIT(2)
6098 #define B_BE_GNT_WL_BB_PWR_VAL BIT(1)
6099 #define B_BE_GNT_WL_BB_PWR_SWCTRL BIT(0)
6100 
6101 #define R_BE_PWR_MACID_PATH_BASE 0x0E500
6102 #define R_BE_PWR_MACID_LMT_BASE 0x0ED00
6103 
6104 #define R_BE_CMAC_FUNC_EN 0x10000
6105 #define R_BE_CMAC_FUNC_EN_C1 0x14000
6106 #define B_BE_CMAC_CRPRT BIT(31)
6107 #define B_BE_CMAC_EN BIT(30)
6108 #define B_BE_CMAC_TXEN BIT(29)
6109 #define B_BE_CMAC_RXEN BIT(28)
6110 #define B_BE_FORCE_RESP_PKTCTL_GCKEN BIT(26)
6111 #define B_BE_FORCE_SIGB_REG_GCKEN BIT(25)
6112 #define B_BE_FORCE_POWER_REG_GCKEN BIT(23)
6113 #define B_BE_FORCE_RMAC_REG_GCKEN BIT(22)
6114 #define B_BE_FORCE_TRXPTCL_REG_GCKEN BIT(21)
6115 #define B_BE_FORCE_TMAC_REG_GCKEN BIT(20)
6116 #define B_BE_FORCE_CMAC_DMA_REG_GCKEN BIT(19)
6117 #define B_BE_FORCE_PTCL_REG_GCKEN BIT(18)
6118 #define B_BE_FORCE_SCHEDULER_RREG_GCKEN BIT(17)
6119 #define B_BE_FORCE_CMAC_COMMON_REG_GCKEN BIT(16)
6120 #define B_BE_FORCE_CMACREG_GCKEN BIT(15)
6121 #define B_BE_TXTIME_EN BIT(8)
6122 #define B_BE_RESP_PKTCTL_EN BIT(7)
6123 #define B_BE_SIGB_EN BIT(6)
6124 #define B_BE_PHYINTF_EN BIT(5)
6125 #define B_BE_CMAC_DMA_EN BIT(4)
6126 #define B_BE_PTCLTOP_EN BIT(3)
6127 #define B_BE_SCHEDULER_EN BIT(2)
6128 #define B_BE_TMAC_EN BIT(1)
6129 #define B_BE_RMAC_EN BIT(0)
6130 #define B_BE_CMAC_FUNC_EN_SET (B_BE_CMAC_EN | B_BE_CMAC_TXEN | B_BE_CMAC_RXEN | \
6131 			       B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN | B_BE_PTCLTOP_EN | \
6132 			       B_BE_SCHEDULER_EN | B_BE_TMAC_EN | B_BE_RMAC_EN | \
6133 			       B_BE_CMAC_CRPRT | B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN | \
6134 			       B_BE_SIGB_EN)
6135 
6136 #define R_BE_CK_EN 0x10004
6137 #define R_BE_CK_EN_C1 0x14004
6138 #define B_BE_CMAC_CKEN BIT(30)
6139 #define B_BE_BCN_P1_P4_CKEN BIT(15)
6140 #define B_BE_BCN_P0MB1_15_CKEN BIT(14)
6141 #define B_BE_TXTIME_CKEN BIT(8)
6142 #define B_BE_RESP_PKTCTL_CKEN BIT(7)
6143 #define B_BE_SIGB_CKEN BIT(6)
6144 #define B_BE_PHYINTF_CKEN BIT(5)
6145 #define B_BE_CMAC_DMA_CKEN BIT(4)
6146 #define B_BE_PTCLTOP_CKEN BIT(3)
6147 #define B_BE_SCHEDULER_CKEN BIT(2)
6148 #define B_BE_TMAC_CKEN BIT(1)
6149 #define B_BE_RMAC_CKEN BIT(0)
6150 #define B_BE_CK_EN_SET (B_BE_CMAC_CKEN | B_BE_PHYINTF_CKEN | B_BE_CMAC_DMA_CKEN | \
6151 			B_BE_PTCLTOP_CKEN | B_BE_SCHEDULER_CKEN | B_BE_TMAC_CKEN | \
6152 			B_BE_RMAC_CKEN | B_BE_TXTIME_CKEN | B_BE_RESP_PKTCTL_CKEN | \
6153 			B_BE_SIGB_CKEN)
6154 
6155 #define R_BE_WMAC_RFMOD 0x10010
6156 #define R_BE_WMAC_RFMOD_C1 0x14010
6157 #define B_BE_CMAC_ASSERTION BIT(31)
6158 #define B_BE_WMAC_RFMOD_MASK GENMASK(2, 0)
6159 #define BE_WMAC_RFMOD_20M 0
6160 #define BE_WMAC_RFMOD_40M 1
6161 #define BE_WMAC_RFMOD_80M 2
6162 #define BE_WMAC_RFMOD_160M 3
6163 #define BE_WMAC_RFMOD_320M 4
6164 
6165 #define R_BE_TX_SUB_BAND_VALUE 0x10088
6166 #define R_BE_TX_SUB_BAND_VALUE_C1 0x14088
6167 #define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16)
6168 #define BE_PRI20_BITMAP_MAX 15
6169 #define B_BE_TXSB_160M_MASK GENMASK(15, 12)
6170 #define S_BE_TXSB_160M_0 0
6171 #define S_BE_TXSB_160M_1 1
6172 #define B_BE_TXSB_80M_MASK GENMASK(11, 8)
6173 #define S_BE_TXSB_80M_0 0
6174 #define S_BE_TXSB_80M_2 2
6175 #define S_BE_TXSB_80M_4 4
6176 #define B_BE_TXSB_40M_MASK GENMASK(7, 4)
6177 #define S_BE_TXSB_40M_0 0
6178 #define S_BE_TXSB_40M_1 1
6179 #define S_BE_TXSB_40M_4 4
6180 #define B_BE_TXSB_20M_MASK GENMASK(3, 0)
6181 #define S_BE_TXSB_20M_8 8
6182 #define S_BE_TXSB_20M_4 4
6183 #define S_BE_TXSB_20M_2 2
6184 
6185 #define R_BE_PTCL_RRSR0 0x1008C
6186 #define R_BE_PTCL_RRSR0_C1 0x1408C
6187 #define B_BE_RRSR_HE_MASK GENMASK(31, 24)
6188 #define B_BE_RRSR_VHT_MASK GENMASK(23, 16)
6189 #define B_BE_RRSR_HT_MASK GENMASK(15, 8)
6190 #define B_BE_RRSR_OFDM_MASK GENMASK(7, 0)
6191 
6192 #define R_BE_PTCL_RRSR1 0x10090
6193 #define R_BE_PTCL_RRSR1_C1 0x14090
6194 #define B_BE_RRSR_EHT_MASK GENMASK(23, 16)
6195 #define B_BE_RRSR_RATE_EN_MASK GENMASK(12, 8)
6196 #define B_BE_RSC_MASK GENMASK(7, 6)
6197 #define B_BE_RRSR_CCK_MASK GENMASK(3, 0)
6198 
6199 #define R_BE_CMAC_ERR_IMR 0x10160
6200 #define R_BE_CMAC_ERR_IMR_C1 0x14160
6201 #define B_BE_CMAC_FW_ERR_IDCT_EN BIT(16)
6202 #define B_BE_PTCL_TX_IDLETO_IDCT_EN BIT(9)
6203 #define B_BE_WMAC_RX_IDLETO_IDCT_EN BIT(8)
6204 #define B_BE_WMAC_TX_ERR_IND_EN BIT(7)
6205 #define B_BE_WMAC_RX_ERR_IND_EN BIT(6)
6206 #define B_BE_TXPWR_CTRL_ERR_IND_EN BIT(5)
6207 #define B_BE_PHYINTF_ERR_IND_EN BIT(4)
6208 #define B_BE_DMA_TOP_ERR_IND_EN BIT(3)
6209 #define B_BE_RESP_PKTCTL_ERR_IND_EN BIT(2)
6210 #define B_BE_PTCL_TOP_ERR_IND_EN BIT(1)
6211 #define B_BE_SCHEDULE_TOP_ERR_IND_EN BIT(0)
6212 
6213 #define R_BE_CMAC_ERR_ISR 0x10164
6214 #define R_BE_CMAC_ERR_ISR_C1 0x14164
6215 #define B_BE_CMAC_FW_ERR_IDCT BIT(16)
6216 #define B_BE_PTCL_TX_IDLETO_IDCT BIT(9)
6217 #define B_BE_WMAC_RX_IDLETO_IDCT BIT(8)
6218 #define B_BE_WMAC_TX_ERR_IND BIT(7)
6219 #define B_BE_WMAC_RX_ERR_IND BIT(6)
6220 #define B_BE_TXPWR_CTRL_ERR_IND BIT(5)
6221 #define B_BE_PHYINTF_ERR_IND BIT(4)
6222 #define B_BE_DMA_TOP_ERR_IND BIT(3)
6223 #define B_BE_RESP_PKTCTL_ERR_IDCT BIT(2)
6224 #define B_BE_PTCL_TOP_ERR_IND BIT(1)
6225 #define B_BE_SCHEDULE_TOP_ERR_IND BIT(0)
6226 
6227 #define R_BE_SER_L0_DBG_CNT 0x10170
6228 #define R_BE_SER_L0_DBG_CNT_C1 0x14170
6229 #define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24)
6230 #define B_BE_SER_L0_DMA_CNT_MASK GENMASK(23, 16)
6231 #define B_BE_SER_L0_PTCL_CNT_MASK GENMASK(15, 8)
6232 #define B_BE_SER_L0_SCH_CNT_MASK GENMASK(7, 0)
6233 
6234 #define R_BE_SER_L0_DBG_CNT1 0x10174
6235 #define R_BE_SER_L0_DBG_CNT1_C1 0x14174
6236 #define B_BE_SER_L0_TMAC_COUNTER_MASK GENMASK(23, 16)
6237 #define B_BE_SER_L0_RMAC_COUNTER_MASK GENMASK(15, 8)
6238 #define B_BE_SER_L0_TXPWR_COUNTER_MASK GENMASK(7, 0)
6239 
6240 #define R_BE_SER_L0_DBG_CNT2 0x10178
6241 #define R_BE_SER_L0_DBG_CNT2_C1 0x14178
6242 
6243 #define R_BE_SER_L0_DBG_CNT3 0x1017C
6244 #define R_BE_SER_L0_DBG_CNT3_C1 0x1417C
6245 #define B_BE_SER_L0_SUBMODULE_BIT31_CNT BIT(31)
6246 #define B_BE_SER_L0_SUBMODULE_BIT30_CNT BIT(30)
6247 #define B_BE_SER_L0_SUBMODULE_BIT29_CNT BIT(29)
6248 #define B_BE_SER_L0_SUBMODULE_BIT28_CNT BIT(28)
6249 #define B_BE_SER_L0_SUBMODULE_BIT27_CNT BIT(27)
6250 #define B_BE_SER_L0_SUBMODULE_BIT26_CNT BIT(26)
6251 #define B_BE_SER_L0_SUBMODULE_BIT25_CNT BIT(25)
6252 #define B_BE_SER_L0_SUBMODULE_BIT24_CNT BIT(24)
6253 #define B_BE_SER_L0_SUBMODULE_BIT23_CNT BIT(23)
6254 #define B_BE_SER_L0_SUBMODULE_BIT22_CNT BIT(22)
6255 #define B_BE_SER_L0_SUBMODULE_BIT21_CNT BIT(21)
6256 #define B_BE_SER_L0_SUBMODULE_BIT20_CNT BIT(20)
6257 #define B_BE_SER_L0_SUBMODULE_BIT19_CNT BIT(19)
6258 #define B_BE_SER_L0_SUBMODULE_BIT18_CNT BIT(18)
6259 #define B_BE_SER_L0_SUBMODULE_BIT17_CNT BIT(17)
6260 #define B_BE_SER_L0_SUBMODULE_BIT16_CNT BIT(16)
6261 #define B_BE_SER_L0_SUBMODULE_BIT15_CNT BIT(15)
6262 #define B_BE_SER_L0_SUBMODULE_BIT14_CNT BIT(14)
6263 #define B_BE_SER_L0_SUBMODULE_BIT13_CNT BIT(13)
6264 #define B_BE_SER_L0_SUBMODULE_BIT12_CNT BIT(12)
6265 #define B_BE_SER_L0_SUBMODULE_BIT11_CNT BIT(11)
6266 #define B_BE_SER_L0_SUBMODULE_BIT10_CNT BIT(10)
6267 #define B_BE_SER_L0_SUBMODULE_BIT9_CNT BIT(9)
6268 #define B_BE_SER_L0_SUBMODULE_BIT8_CNT BIT(8)
6269 #define B_BE_SER_L0_SUBMODULE_BIT7_CNT BIT(7)
6270 #define B_BE_SER_L0_SUBMODULE_BIT6_CNT BIT(6)
6271 #define B_BE_SER_L0_SUBMODULE_BIT5_CNT BIT(5)
6272 #define B_BE_SER_L0_SUBMODULE_BIT4_CNT BIT(4)
6273 #define B_BE_SER_L0_SUBMODULE_BIT3_CNT BIT(3)
6274 #define B_BE_SER_L0_SUBMODULE_BIT2_CNT BIT(2)
6275 #define B_BE_SER_L0_SUBMODULE_BIT1_CNT BIT(1)
6276 #define B_BE_SER_L0_SUBMODULE_BIT0_CNT BIT(0)
6277 
6278 #define R_BE_PORT_0_TSF_SYNC 0x102A0
6279 #define R_BE_PORT_0_TSF_SYNC_C1 0x142A0
6280 #define B_BE_P0_SYNC_NOW_P BIT(30)
6281 #define B_BE_P0_SYNC_ONCE_P BIT(29)
6282 #define B_BE_P0_AUTO_SYNC BIT(28)
6283 #define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24)
6284 #define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0)
6285 
6286 #define R_BE_EDCA_BCNQ_PARAM 0x10324
6287 #define R_BE_EDCA_BCNQ_PARAM_C1 0x14324
6288 #define B_BE_BCNQ_CW_MASK GENMASK(31, 24)
6289 #define B_BE_BCNQ_AIFS_MASK GENMASK(23, 16)
6290 #define BCN_IFS_25US 0x19
6291 #define B_BE_PIFS_MASK GENMASK(15, 8)
6292 #define B_BE_FORCE_BCN_IFS_MASK GENMASK(7, 0)
6293 
6294 #define R_BE_PREBKF_CFG_0 0x10338
6295 #define R_BE_PREBKF_CFG_0_C1 0x14338
6296 #define B_BE_100NS_TIME_MASK GENMASK(28, 24)
6297 #define B_BE_RX_AIR_END_TIME_MASK GENMASK(22, 16)
6298 #define B_BE_MACTX_LATENCY_MASK GENMASK(10, 8)
6299 #define B_BE_PREBKF_TIME_MASK GENMASK(4, 0)
6300 
6301 #define R_BE_PREBKF_CFG_1 0x1033C
6302 #define R_BE_PREBKF_CFG_1_C1 0x1433C
6303 #define B_BE_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(31, 24)
6304 #define B_BE_SIFS_PREBKF_MASK GENMASK(23, 16)
6305 #define B_BE_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
6306 #define B_BE_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
6307 
6308 #define R_BE_CCA_CFG_0 0x10340
6309 #define R_BE_CCA_CFG_0_C1 0x14340
6310 #define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24)
6311 #define B_BE_EDCCA_SEC160_EN BIT(23)
6312 #define B_BE_EDCCA_SEC80_EN BIT(22)
6313 #define B_BE_EDCCA_SEC40_EN BIT(21)
6314 #define B_BE_EDCCA_SEC20_EN BIT(20)
6315 #define B_BE_SEC160_EN BIT(19)
6316 #define B_BE_CCA_BITMAP_EN BIT(18)
6317 #define B_BE_TXPKTCTL_RST_EDCA_EN BIT(17)
6318 #define B_BE_WMAC_RST_EDCA_EN BIT(16)
6319 #define B_BE_TXFAIL_BRK_TXOP_EN BIT(11)
6320 #define B_BE_EDCCA_PER20_BITMAP_SIFS_EN BIT(10)
6321 #define B_BE_NO_GNT_WL_BRK_TXOP_EN BIT(9)
6322 #define B_BE_NAV_BRK_TXOP_EN BIT(8)
6323 #define B_BE_TX_NAV_EN BIT(7)
6324 #define B_BE_BCN_IGNORE_EDCCA BIT(6)
6325 #define B_BE_NO_GNT_WL_EN BIT(5)
6326 #define B_BE_EDCCA_EN BIT(4)
6327 #define B_BE_SEC80_EN BIT(3)
6328 #define B_BE_SEC40_EN BIT(2)
6329 #define B_BE_SEC20_EN BIT(1)
6330 #define B_BE_CCA_EN BIT(0)
6331 
6332 #define R_BE_CTN_CFG_0 0x1034C
6333 #define R_BE_CTN_CFG_0_C1 0x1434C
6334 #define B_BE_OTHER_LINK_BKF_BLK_TX_THD_MASK GENMASK(30, 24)
6335 #define B_BE_CCK_SIFS_COMP_MASK GENMASK(22, 16)
6336 #define B_BE_PIFS_TIMEUNIT_MASK GENMASK(15, 14)
6337 #define B_BE_PREBKF_TIME_NONAC_MASK GENMASK(12, 8)
6338 #define B_BE_SR_TX_EN BIT(2)
6339 #define B_BE_NAV_BLK_MGQ BIT(1)
6340 #define B_BE_NAV_BLK_HGQ BIT(0)
6341 
6342 #define R_BE_MUEDCA_BE_PARAM_0 0x10350
6343 #define R_BE_MUEDCA_BK_PARAM_0 0x10354
6344 #define R_BE_MUEDCA_VI_PARAM_0 0x10358
6345 #define R_BE_MUEDCA_VO_PARAM_0 0x1035C
6346 
6347 #define R_BE_MUEDCA_EN 0x10370
6348 #define R_BE_MUEDCA_EN_C1 0x14370
6349 #define B_BE_SIFS_TIMEOUT_TB_T2_MASK GENMASK(30, 24)
6350 #define B_BE_SIFS_MACTXEN_TB_T1_MASK GENMASK(22, 16)
6351 #define B_BE_MUEDCA_WMM_SEL BIT(8)
6352 #define B_BE_SET_MUEDCATIMER_TF_MASK GENMASK(5, 4)
6353 #define B_BE_SET_MUEDCATIMER_TF_0 BIT(4)
6354 #define B_BE_MUEDCA_EN_MASK GENMASK(1, 0)
6355 #define B_BE_MUEDCA_EN_0 BIT(0)
6356 
6357 #define R_BE_CTN_DRV_TXEN 0x10398
6358 #define R_BE_CTN_DRV_TXEN_C1 0x14398
6359 #define B_BE_CTN_TXEN_TWT_3 BIT(17)
6360 #define B_BE_CTN_TXEN_TWT_2 BIT(16)
6361 #define B_BE_CTN_TXEN_TWT_1 BIT(15)
6362 #define B_BE_CTN_TXEN_TWT_0 BIT(14)
6363 #define B_BE_CTN_TXEN_ULQ BIT(13)
6364 #define B_BE_CTN_TXEN_BCNQ BIT(12)
6365 #define B_BE_CTN_TXEN_HGQ BIT(11)
6366 #define B_BE_CTN_TXEN_CPUMGQ BIT(10)
6367 #define B_BE_CTN_TXEN_MGQ1 BIT(9)
6368 #define B_BE_CTN_TXEN_MGQ BIT(8)
6369 #define B_BE_CTN_TXEN_VO_1 BIT(7)
6370 #define B_BE_CTN_TXEN_VI_1 BIT(6)
6371 #define B_BE_CTN_TXEN_BK_1 BIT(5)
6372 #define B_BE_CTN_TXEN_BE_1 BIT(4)
6373 #define B_BE_CTN_TXEN_VO_0 BIT(3)
6374 #define B_BE_CTN_TXEN_VI_0 BIT(2)
6375 #define B_BE_CTN_TXEN_BK_0 BIT(1)
6376 #define B_BE_CTN_TXEN_BE_0 BIT(0)
6377 #define B_BE_CTN_TXEN_ALL_MASK GENMASK(17, 0)
6378 
6379 #define R_BE_TB_CHK_CCA_NAV 0x103AC
6380 #define R_BE_TB_CHK_CCA_NAV_C1 0x143AC
6381 #define B_BE_TB_CHK_TX_NAV BIT(15)
6382 #define B_BE_TB_CHK_INTRA_NAV BIT(14)
6383 #define B_BE_TB_CHK_BASIC_NAV BIT(13)
6384 #define B_BE_TB_CHK_NO_GNT_WL BIT(12)
6385 #define B_BE_TB_CHK_EDCCA_S160 BIT(11)
6386 #define B_BE_TB_CHK_EDCCA_S80 BIT(10)
6387 #define B_BE_TB_CHK_EDCCA_S40 BIT(9)
6388 #define B_BE_TB_CHK_EDCCA_S20 BIT(8)
6389 #define B_BE_TB_CHK_CCA_S160 BIT(7)
6390 #define B_BE_TB_CHK_CCA_S80 BIT(6)
6391 #define B_BE_TB_CHK_CCA_S40 BIT(5)
6392 #define B_BE_TB_CHK_CCA_S20 BIT(4)
6393 #define B_BE_TB_CHK_EDCCA_BITMAP BIT(3)
6394 #define B_BE_TB_CHK_CCA_BITMAP BIT(2)
6395 #define B_BE_TB_CHK_EDCCA_P20 BIT(1)
6396 #define B_BE_TB_CHK_CCA_P20 BIT(0)
6397 
6398 #define R_BE_HE_SIFS_CHK_CCA_NAV 0x103B4
6399 #define R_BE_HE_SIFS_CHK_CCA_NAV_C1 0x143B4
6400 #define B_BE_HE_SIFS_CHK_TX_NAV BIT(15)
6401 #define B_BE_HE_SIFS_CHK_INTRA_NAV BIT(14)
6402 #define B_BE_HE_SIFS_CHK_BASIC_NAV BIT(13)
6403 #define B_BE_HE_SIFS_CHK_NO_GNT_WL BIT(12)
6404 #define B_BE_HE_SIFS_CHK_EDCCA_S160 BIT(11)
6405 #define B_BE_HE_SIFS_CHK_EDCCA_S80 BIT(10)
6406 #define B_BE_HE_SIFS_CHK_EDCCA_S40 BIT(9)
6407 #define B_BE_HE_SIFS_CHK_EDCCA_S20 BIT(8)
6408 #define B_BE_HE_SIFS_CHK_CCA_S160 BIT(7)
6409 #define B_BE_HE_SIFS_CHK_CCA_S80 BIT(6)
6410 #define B_BE_HE_SIFS_CHK_CCA_S40 BIT(5)
6411 #define B_BE_HE_SIFS_CHK_CCA_S20 BIT(4)
6412 #define B_BE_HE_SIFS_CHK_EDCCA_BITMAP BIT(3)
6413 #define B_BE_HE_SIFS_CHK_CCA_BITMAP BIT(2)
6414 #define B_BE_HE_SIFS_CHK_EDCCA_P20 BIT(1)
6415 #define B_BE_HE_SIFS_CHK_CCA_P20 BIT(0)
6416 
6417 #define R_BE_HE_CTN_CHK_CCA_NAV 0x103C4
6418 #define R_BE_HE_CTN_CHK_CCA_NAV_C1 0x143C4
6419 #define B_BE_HE_CTN_CHK_TX_NAV BIT(15)
6420 #define B_BE_HE_CTN_CHK_INTRA_NAV BIT(14)
6421 #define B_BE_HE_CTN_CHK_BASIC_NAV BIT(13)
6422 #define B_BE_HE_CTN_CHK_NO_GNT_WL BIT(12)
6423 #define B_BE_HE_CTN_CHK_EDCCA_S160 BIT(11)
6424 #define B_BE_HE_CTN_CHK_EDCCA_S80 BIT(10)
6425 #define B_BE_HE_CTN_CHK_EDCCA_S40 BIT(9)
6426 #define B_BE_HE_CTN_CHK_EDCCA_S20 BIT(8)
6427 #define B_BE_HE_CTN_CHK_CCA_S160 BIT(7)
6428 #define B_BE_HE_CTN_CHK_CCA_S80 BIT(6)
6429 #define B_BE_HE_CTN_CHK_CCA_S40 BIT(5)
6430 #define B_BE_HE_CTN_CHK_CCA_S20 BIT(4)
6431 #define B_BE_HE_CTN_CHK_EDCCA_BITMAP BIT(3)
6432 #define B_BE_HE_CTN_CHK_CCA_BITMAP BIT(2)
6433 #define B_BE_HE_CTN_CHK_EDCCA_P20 BIT(1)
6434 #define B_BE_HE_CTN_CHK_CCA_P20 BIT(0)
6435 
6436 #define R_BE_SCHEDULE_ERR_IMR 0x103E8
6437 #define R_BE_SCHEDULE_ERR_IMR_C1 0x143E8
6438 #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
6439 #define B_BE_SCHEDULE_ERR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN
6440 #define B_BE_SCHEDULE_ERR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN
6441 
6442 #define R_BE_SCHEDULE_ERR_ISR 0x103EC
6443 #define R_BE_SCHEDULE_ERR_ISR_C1 0x143EC
6444 #define B_BE_SORT_NON_IDLE_ERR_INT BIT(1)
6445 #define B_BE_FSM_TIMEOUT_ERR_INT BIT(0)
6446 
6447 #define R_BE_PORT_CFG_P0 0x10400
6448 #define R_BE_PORT_CFG_P0_C1 0x14400
6449 #define B_BE_BCN_ERLY_SORT_EN_P0 BIT(18)
6450 #define B_BE_PROHIB_END_CAL_EN_P0 BIT(17)
6451 #define B_BE_BRK_SETUP_P0 BIT(16)
6452 #define B_BE_TBTT_UPD_SHIFT_SEL_P0 BIT(15)
6453 #define B_BE_BCN_DROP_ALLOW_P0 BIT(14)
6454 #define B_BE_TBTT_PROHIB_EN_P0 BIT(13)
6455 #define B_BE_BCNTX_EN_P0 BIT(12)
6456 #define B_BE_NET_TYPE_P0_MASK GENMASK(11, 10)
6457 #define B_BE_BCN_FORCETX_EN_P0 BIT(9)
6458 #define B_BE_TXBCN_BTCCA_EN_P0 BIT(8)
6459 #define B_BE_BCNERR_CNT_EN_P0 BIT(7)
6460 #define B_BE_BCN_AGRES_P0 BIT(6)
6461 #define B_BE_TSFTR_RST_P0 BIT(5)
6462 #define B_BE_RX_BSSID_FIT_EN_P0 BIT(4)
6463 #define B_BE_TSF_UDT_EN_P0 BIT(3)
6464 #define B_BE_PORT_FUNC_EN_P0 BIT(2)
6465 #define B_BE_TXBCN_RPT_EN_P0 BIT(1)
6466 #define B_BE_RXBCN_RPT_EN_P0 BIT(0)
6467 
6468 #define R_BE_TBTT_PROHIB_P0 0x10404
6469 #define R_BE_TBTT_PROHIB_P0_C1 0x14404
6470 #define B_BE_TBTT_HOLD_P0_MASK GENMASK(27, 16)
6471 #define B_BE_TBTT_SETUP_P0_MASK GENMASK(7, 0)
6472 
6473 #define R_BE_BCN_AREA_P0 0x10408
6474 #define R_BE_BCN_AREA_P0_C1 0x14408
6475 #define B_BE_BCN_MSK_AREA_P0_MSK 0xfff
6476 #define B_BE_BCN_CTN_AREA_P0_MASK GENMASK(11, 0)
6477 
6478 #define R_BE_BCNERLYINT_CFG_P0 0x1040C
6479 #define R_BE_BCNERLYINT_CFG_P0_C1 0x1440C
6480 #define B_BE_BCNERLY_P0_MASK GENMASK(11, 0)
6481 
6482 #define R_BE_TBTTERLYINT_CFG_P0 0x1040E
6483 #define R_BE_TBTTERLYINT_CFG_P0_C1 0x1440E
6484 #define B_BE_TBTTERLY_P0_MASK GENMASK(11, 0)
6485 
6486 #define R_BE_TBTT_AGG_P0 0x10412
6487 #define R_BE_TBTT_AGG_P0_C1 0x14412
6488 #define B_BE_TBTT_AGG_NUM_P0_MASK GENMASK(15, 8)
6489 
6490 #define R_BE_BCN_SPACE_CFG_P0 0x10414
6491 #define R_BE_BCN_SPACE_CFG_P0_C1 0x14414
6492 #define B_BE_SUB_BCN_SPACE_P0_MASK GENMASK(23, 16)
6493 #define B_BE_BCN_SPACE_P0_MASK GENMASK(15, 0)
6494 
6495 #define R_BE_BCN_FORCETX_P0 0x10418
6496 #define R_BE_BCN_FORCETX_P0_C1 0x14418
6497 #define B_BE_FORCE_BCN_NUM_P0_MASK GENMASK(15, 8)
6498 #define B_BE_BCN_MAX_ERR_P0_MASK GENMASK(7, 0)
6499 
6500 #define R_BE_BCN_ERR_CNT_P0 0x10420
6501 #define R_BE_BCN_ERR_CNT_P0_C1 0x14420
6502 #define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24)
6503 #define B_BE_BCN_ERR_CNT_NAV_P0_MASK GENMASK(23, 16)
6504 #define B_BE_BCN_ERR_CNT_EDCCA_P0_MASK GENMASK(15, 8)
6505 #define B_BE_BCN_ERR_CNT_CCA_P0_MASK GENMASK(7, 0)
6506 
6507 #define R_BE_BCN_ERR_FLAG_P0 0x10424
6508 #define R_BE_BCN_ERR_FLAG_P0_C1 0x14424
6509 #define B_BE_BCN_ERR_FLAG_SRCHEND_P0 BIT(3)
6510 #define B_BE_BCN_ERR_FLAG_INVALID_P0 BIT(2)
6511 #define B_BE_BCN_ERR_FLAG_CMP_P0 BIT(1)
6512 #define B_BE_BCN_ERR_FLAG_LOCK_P0 BIT(0)
6513 
6514 #define R_BE_DTIM_CTRL_P0 0x10426
6515 #define R_BE_DTIM_CTRL_P0_C1 0x14426
6516 #define B_BE_DTIM_NUM_P0_MASK GENMASK(15, 8)
6517 #define B_BE_DTIM_CURRCNT_P0_MASK GENMASK(7, 0)
6518 
6519 #define R_BE_TBTT_SHIFT_P0 0x10428
6520 #define R_BE_TBTT_SHIFT_P0_C1 0x14428
6521 #define B_BE_TBTT_SHIFT_OFST_P0_SH 0
6522 #define B_BE_TBTT_SHIFT_OFST_P0_MSK 0xfff
6523 
6524 #define R_BE_BCN_CNT_TMR_P0 0x10434
6525 #define R_BE_BCN_CNT_TMR_P0_C1 0x14434
6526 #define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0)
6527 
6528 #define R_BE_TSFTR_LOW_P0 0x10438
6529 #define R_BE_TSFTR_LOW_P0_C1 0x14438
6530 #define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0)
6531 
6532 #define R_BE_TSFTR_HIGH_P0 0x1043C
6533 #define R_BE_TSFTR_HIGH_P0_C1 0x1443C
6534 #define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0)
6535 
6536 #define R_BE_BCN_DROP_ALL0 0x10560
6537 
6538 #define R_BE_MBSSID_CTRL 0x10568
6539 #define R_BE_MBSSID_CTRL_C1 0x14568
6540 #define B_BE_MBSSID_MODE_SEL BIT(20)
6541 #define B_BE_P0MB_NUM_MASK GENMASK(19, 16)
6542 #define B_BE_P0MB15_EN BIT(15)
6543 #define B_BE_P0MB14_EN BIT(14)
6544 #define B_BE_P0MB13_EN BIT(13)
6545 #define B_BE_P0MB12_EN BIT(12)
6546 #define B_BE_P0MB11_EN BIT(11)
6547 #define B_BE_P0MB10_EN BIT(10)
6548 #define B_BE_P0MB9_EN BIT(9)
6549 #define B_BE_P0MB8_EN BIT(8)
6550 #define B_BE_P0MB7_EN BIT(7)
6551 #define B_BE_P0MB6_EN BIT(6)
6552 #define B_BE_P0MB5_EN BIT(5)
6553 #define B_BE_P0MB4_EN BIT(4)
6554 #define B_BE_P0MB3_EN BIT(3)
6555 #define B_BE_P0MB2_EN BIT(2)
6556 #define B_BE_P0MB1_EN BIT(1)
6557 
6558 #define R_BE_P0MB_HGQ_WINDOW_CFG_0 0x10590
6559 #define R_BE_P0MB_HGQ_WINDOW_CFG_0_C1 0x14590
6560 #define R_BE_PORT_HGQ_WINDOW_CFG 0x105A0
6561 #define R_BE_PORT_HGQ_WINDOW_CFG_C1 0x145A0
6562 
6563 #define R_BE_PTCL_COMMON_SETTING_0 0x10800
6564 #define R_BE_PTCL_COMMON_SETTING_0_C1 0x14800
6565 #define B_BE_PCIE_MODE_MASK GENMASK(15, 14)
6566 #define B_BE_CPUMGQ_LIFETIME_EN BIT(8)
6567 #define B_BE_MGQ_LIFETIME_EN BIT(7)
6568 #define B_BE_LIFETIME_EN BIT(6)
6569 #define B_BE_DIS_PTCL_CLK_GATING BIT(5)
6570 #define B_BE_PTCL_TRIGGER_SS_EN_UL BIT(4)
6571 #define B_BE_PTCL_TRIGGER_SS_EN_1 BIT(3)
6572 #define B_BE_PTCL_TRIGGER_SS_EN_0 BIT(2)
6573 #define B_BE_CMAC_TX_MODE_1 BIT(1)
6574 #define B_BE_CMAC_TX_MODE_0 BIT(0)
6575 
6576 #define R_BE_TB_PPDU_CTRL 0x1080C
6577 #define R_BE_TB_PPDU_CTRL_C1 0x1480C
6578 #define B_BE_TB_PPDU_BK_DIS BIT(15)
6579 #define B_BE_TB_PPDU_BE_DIS BIT(14)
6580 #define B_BE_TB_PPDU_VI_DIS BIT(13)
6581 #define B_BE_TB_PPDU_VO_DIS BIT(12)
6582 #define B_BE_QOSNULL_UPD_MUEDCA_EN BIT(3)
6583 #define B_BE_TB_BYPASS_TXPWR BIT(2)
6584 #define B_BE_SW_PREFER_AC_MASK GENMASK(1, 0)
6585 
6586 #define R_BE_AMPDU_AGG_LIMIT 0x10810
6587 #define R_BE_AMPDU_AGG_LIMIT_C1 0x14810
6588 #define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
6589 #define AMPDU_MAX_TIME 0x9E
6590 #define B_BE_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
6591 #define B_BE_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
6592 #define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0)
6593 
6594 #define R_BE_AGG_LEN_HT_0 0x10814
6595 #define R_BE_AGG_LEN_HT_0_C1 0x14814
6596 #define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
6597 #define B_BE_RTS_TXTIME_TH_MASK GENMASK(15, 8)
6598 #define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0)
6599 
6600 #define R_BE_SIFS_SETTING 0x10824
6601 #define R_BE_SIFS_SETTING_C1 0x14824
6602 #define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
6603 #define B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
6604 #define B_BE_HW_CTS2SELF_EN BIT(16)
6605 #define B_BE_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
6606 #define B_BE_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
6607 
6608 #define R_BE_TXRATE_CHK 0x10828
6609 #define R_BE_TXRATE_CHK_C1 0x14828
6610 #define B_BE_LATENCY_PADDING_PKT_TH_MASK GENMASK(31, 24)
6611 #define B_BE_PLCP_FETCH_BUFF_MASK GENMASK(23, 16)
6612 #define B_BE_OFDM_CCK_ERR_PROC BIT(6)
6613 #define B_BE_PKT_LAST_TX BIT(5)
6614 #define B_BE_BAND_MODE BIT(4)
6615 #define B_BE_MAX_TXNSS_MASK GENMASK(3, 2)
6616 #define B_BE_RTS_LIMIT_IN_OFDM6 BIT(1)
6617 #define B_BE_CHECK_CCK_EN BIT(0)
6618 
6619 #define R_BE_MBSSID_DROP_0 0x1083C
6620 #define R_BE_MBSSID_DROP_0_C1 0x1483C
6621 #define B_BE_GI_LTF_FB_SEL BIT(30)
6622 #define B_BE_RATE_SEL_MASK GENMASK(29, 24)
6623 #define B_BE_PORT_DROP_4_0_MASK GENMASK(20, 16)
6624 #define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
6625 
6626 #define R_BE_BT_PLT 0x1087C
6627 #define R_BE_BT_PLT_C1 0x1487C
6628 #define B_BE_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
6629 #define B_BE_BT_PLT_RST BIT(9)
6630 #define B_BE_PLT_EN BIT(8)
6631 #define B_BE_RX_PLT_GNT_LTE_RX BIT(7)
6632 #define B_BE_RX_PLT_GNT_BT_RX BIT(6)
6633 #define B_BE_RX_PLT_GNT_BT_TX BIT(5)
6634 #define B_BE_RX_PLT_GNT_WL BIT(4)
6635 #define B_BE_TX_PLT_GNT_LTE_RX BIT(3)
6636 #define B_BE_TX_PLT_GNT_BT_RX BIT(2)
6637 #define B_BE_TX_PLT_GNT_BT_TX BIT(1)
6638 #define B_BE_TX_PLT_GNT_WL BIT(0)
6639 
6640 #define R_BE_PTCL_BSS_COLOR_0 0x108A0
6641 #define R_BE_PTCL_BSS_COLOR_0_C1 0x148A0
6642 #define B_BE_BSS_COLOB_BE_PORT_3_MASK GENMASK(29, 24)
6643 #define B_BE_BSS_COLOB_BE_PORT_2_MASK GENMASK(21, 16)
6644 #define B_BE_BSS_COLOB_BE_PORT_1_MASK GENMASK(13, 8)
6645 #define B_BE_BSS_COLOB_BE_PORT_0_MASK GENMASK(5, 0)
6646 
6647 #define R_BE_PTCL_BSS_COLOR_1 0x108A4
6648 #define R_BE_PTCL_BSS_COLOR_1_C1 0x148A4
6649 #define B_BE_BSS_COLOB_BE_PORT_4_MASK GENMASK(5, 0)
6650 
6651 #define R_BE_PTCL_IMR_2 0x108B8
6652 #define R_BE_PTCL_IMR_2_C1 0x148B8
6653 #define B_BE_NO_TRX_TIMEOUT_IMR BIT(1)
6654 #define B_BE_TX_IDLE_TIMEOUT_IMR BIT(0)
6655 #define B_BE_PTCL_IMR_2_CLR B_BE_TX_IDLE_TIMEOUT_IMR
6656 #define B_BE_PTCL_IMR_2_SET 0
6657 
6658 #define R_BE_PTCL_IMR0 0x108C0
6659 #define R_BE_PTCL_IMR0_C1 0x148C0
6660 #define B_BE_PTCL_ERROR_FLAG_IMR BIT(31)
6661 #define B_BE_FSM1_TIMEOUT_ERR_INT_EN BIT(1)
6662 #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
6663 #define B_BE_PTCL_IMR0_CLR (B_BE_FSM_TIMEOUT_ERR_INT_EN | \
6664 			    B_BE_FSM1_TIMEOUT_ERR_INT_EN | \
6665 			    B_BE_PTCL_ERROR_FLAG_IMR)
6666 #define B_BE_PTCL_IMR0_SET (B_BE_FSM_TIMEOUT_ERR_INT_EN | \
6667 			    B_BE_FSM1_TIMEOUT_ERR_INT_EN | \
6668 			    B_BE_PTCL_ERROR_FLAG_IMR)
6669 
6670 #define R_BE_PTCL_ISR0 0x108C4
6671 #define R_BE_PTCL_ISR0_C1 0x148C4
6672 #define B_BE_PTCL_ERROR_FLAG_ISR BIT(31)
6673 #define B_BE_FSM1_TIMEOUT_ERR BIT(1)
6674 #define B_BE_FSM_TIMEOUT_ERR BIT(0)
6675 
6676 #define R_BE_PTCL_IMR1 0x108C8
6677 #define R_BE_PTCL_IMR1_C1 0x148C8
6678 #define B_BE_F2PCMD_PKTID_IMR BIT(30)
6679 #define B_BE_F2PCMD_RD_PKTID_IMR BIT(29)
6680 #define B_BE_F2PCMD_ASSIGN_PKTID_IMR BIT(28)
6681 #define B_BE_F2PCMD_USER_ALLC_IMR BIT(27)
6682 #define B_BE_RX_SPF_U0_PKTID_IMR BIT(26)
6683 #define B_BE_TX_SPF_U1_PKTID_IMR BIT(25)
6684 #define B_BE_TX_SPF_U2_PKTID_IMR BIT(24)
6685 #define B_BE_TX_SPF_U3_PKTID_IMR BIT(23)
6686 #define B_BE_TX_RECORD_PKTID_IMR BIT(22)
6687 #define B_BE_TWTSP_QSEL_IMR BIT(14)
6688 #define B_BE_F2P_RLS_CTN_SEL_IMR BIT(13)
6689 #define B_BE_BCNQ_ORDER_IMR BIT(12)
6690 #define B_BE_Q_PKTID_IMR BIT(11)
6691 #define B_BE_D_PKTID_IMR BIT(10)
6692 #define B_BE_TXPRT_FULL_DROP_IMR BIT(9)
6693 #define B_BE_F2PCMDRPT_FULL_DROP_IMR BIT(8)
6694 #define B_BE_PTCL_IMR1_CLR (B_BE_F2PCMDRPT_FULL_DROP_IMR | \
6695 			    B_BE_TXPRT_FULL_DROP_IMR | \
6696 			    B_BE_D_PKTID_IMR | \
6697 			    B_BE_Q_PKTID_IMR | \
6698 			    B_BE_BCNQ_ORDER_IMR | \
6699 			    B_BE_F2P_RLS_CTN_SEL_IMR | \
6700 			    B_BE_TWTSP_QSEL_IMR | \
6701 			    B_BE_TX_RECORD_PKTID_IMR | \
6702 			    B_BE_TX_SPF_U3_PKTID_IMR | \
6703 			    B_BE_TX_SPF_U2_PKTID_IMR | \
6704 			    B_BE_TX_SPF_U1_PKTID_IMR | \
6705 			    B_BE_RX_SPF_U0_PKTID_IMR | \
6706 			    B_BE_F2PCMD_USER_ALLC_IMR | \
6707 			    B_BE_F2PCMD_ASSIGN_PKTID_IMR | \
6708 			    B_BE_F2PCMD_RD_PKTID_IMR | \
6709 			    B_BE_F2PCMD_PKTID_IMR)
6710 #define B_BE_PTCL_IMR1_SET B_BE_F2PCMD_USER_ALLC_IMR
6711 
6712 #define R_BE_PTCL_ISR1 0x108CC
6713 #define R_BE_PTCL_ISR1_C1 0x148CC
6714 #define B_BE_F2PCMD_PKTID_ERR BIT(30)
6715 #define B_BE_F2PCMD_RD_PKTID_ERR BIT(29)
6716 #define B_BE_F2PCMD_ASSIGN_PKTID_ERR BIT(28)
6717 #define B_BE_F2PCMD_USER_ALLC_ERR BIT(27)
6718 #define B_BE_RX_SPF_U0_PKTID_ERR BIT(26)
6719 #define B_BE_TX_SPF_U1_PKTID_ERR BIT(25)
6720 #define B_BE_TX_SPF_U2_PKTID_ERR BIT(24)
6721 #define B_BE_TX_SPF_U3_PKTID_ERR BIT(23)
6722 #define B_BE_TX_RECORD_PKTID_ERR BIT(22)
6723 #define B_BE_TWTSP_QSEL_ERR BIT(14)
6724 #define B_BE_F2P_RLS_CTN_SEL_ERR BIT(13)
6725 #define B_BE_BCNQ_ORDER_ERR BIT(12)
6726 #define B_BE_Q_PKTID_ERR BIT(11)
6727 #define B_BE_D_PKTID_ERR BIT(10)
6728 #define B_BE_TXPRT_FULL_DROP_ERR BIT(9)
6729 #define B_BE_F2PCMDRPT_FULL_DROP_ERR BIT(8)
6730 
6731 #define R_BE_PTCL_FSM_MON 0x108E8
6732 #define R_BE_PTCL_FSM_MON_C1 0x148E8
6733 #define B_BE_PTCL_FSM2_TO_MODE BIT(30)
6734 #define B_BE_PTCL_FSM2_TO_THR_MASK GENMASK(29, 24)
6735 #define B_BE_PTCL_FSM1_TO_MODE BIT(22)
6736 #define B_BE_PTCL_FSM1_TO_THR_MASK GENMASK(21, 16)
6737 #define B_BE_PTCL_FSM0_TO_MODE BIT(14)
6738 #define B_BE_PTCL_FSM0_TO_THR_MASK GENMASK(13, 8)
6739 #define B_BE_PTCL_TX_ARB_TO_MODE BIT(6)
6740 #define B_BE_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
6741 
6742 #define R_BE_PTCL_TX_CTN_SEL 0x108EC
6743 #define R_BE_PTCL_TX_CTN_SEL_C1 0x148EC
6744 #define B_BE_PTCL_TXOP_STAT BIT(8)
6745 #define B_BE_PTCL_BUSY BIT(7)
6746 #define B_BE_PTCL_DROP BIT(5)
6747 #define B_BE_PTCL_TX_QUEUE_IDX_MASK GENMASK(4, 0)
6748 
6749 #define R_BE_PTCL_DBG_INFO 0x108F0
6750 
6751 #define R_BE_PTCL_DBG 0x108F4
6752 
6753 #define R_BE_RX_ERROR_FLAG 0x10C00
6754 #define R_BE_RX_ERROR_FLAG_C1 0x14C00
6755 #define B_BE_RX_CSI_NOT_RELEASE_ERROR BIT(31)
6756 #define B_BE_RX_GET_NULL_PKT_ERROR BIT(30)
6757 #define B_BE_RX_RU0_FSM_HANG_ERROR BIT(29)
6758 #define B_BE_RX_RU1_FSM_HANG_ERROR BIT(28)
6759 #define B_BE_RX_RU2_FSM_HANG_ERROR BIT(27)
6760 #define B_BE_RX_RU3_FSM_HANG_ERROR BIT(26)
6761 #define B_BE_RX_RU4_FSM_HANG_ERROR BIT(25)
6762 #define B_BE_RX_RU5_FSM_HANG_ERROR BIT(24)
6763 #define B_BE_RX_RU6_FSM_HANG_ERROR BIT(23)
6764 #define B_BE_RX_RU7_FSM_HANG_ERROR BIT(22)
6765 #define B_BE_RX_RXSTS_FSM_HANG_ERROR BIT(21)
6766 #define B_BE_RX_CSI_FSM_HANG_ERROR BIT(20)
6767 #define B_BE_RX_TXRPT_FSM_HANG_ERROR BIT(19)
6768 #define B_BE_RX_F2PCMD_FSM_HANG_ERROR BIT(18)
6769 #define B_BE_RX_RU0_ZERO_LENGTH_ERROR BIT(17)
6770 #define B_BE_RX_RU1_ZERO_LENGTH_ERROR BIT(16)
6771 #define B_BE_RX_RU2_ZERO_LENGTH_ERROR BIT(15)
6772 #define B_BE_RX_RU3_ZERO_LENGTH_ERROR BIT(14)
6773 #define B_BE_RX_RU4_ZERO_LENGTH_ERROR BIT(13)
6774 #define B_BE_RX_RU5_ZERO_LENGTH_ERROR BIT(12)
6775 #define B_BE_RX_RU6_ZERO_LENGTH_ERROR BIT(11)
6776 #define B_BE_RX_RU7_ZERO_LENGTH_ERROR BIT(10)
6777 #define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR BIT(9)
6778 #define B_BE_RX_CSI_ZERO_LENGTH_ERROR BIT(8)
6779 #define B_BE_PLE_DATA_OPT_FSM_HANG BIT(7)
6780 #define B_BE_PLE_RXDATA_REQUEST_BUFFER_FSM_HANG BIT(6)
6781 #define B_BE_PLE_TXRPT_REQUEST_BUFFER_FSM_HANG BIT(5)
6782 #define B_BE_PLE_WD_OPT_FSM_HANG BIT(4)
6783 #define B_BE_PLE_ENQ_FSM_HANG BIT(3)
6784 #define B_BE_RXDATA_ENQUE_ORDER_ERROR BIT(2)
6785 #define B_BE_RXSTS_ENQUE_ORDER_ERROR BIT(1)
6786 #define B_BE_RX_CSI_PKT_NUM_ERROR BIT(0)
6787 
6788 #define R_BE_RX_ERROR_FLAG_IMR 0x10C04
6789 #define R_BE_RX_ERROR_FLAG_IMR_C1 0x14C04
6790 #define B_BE_RX_CSI_NOT_RELEASE_ERROR_IMR BIT(31)
6791 #define B_BE_RX_GET_NULL_PKT_ERROR_IMR BIT(30)
6792 #define B_BE_RX_RU0_FSM_HANG_ERROR_IMR BIT(29)
6793 #define B_BE_RX_RU1_FSM_HANG_ERROR_IMR BIT(28)
6794 #define B_BE_RX_RU2_FSM_HANG_ERROR_IMR BIT(27)
6795 #define B_BE_RX_RU3_FSM_HANG_ERROR_IMR BIT(26)
6796 #define B_BE_RX_RU4_FSM_HANG_ERROR_IMR BIT(25)
6797 #define B_BE_RX_RU5_FSM_HANG_ERROR_IMR BIT(24)
6798 #define B_BE_RX_RU6_FSM_HANG_ERROR_IMR BIT(23)
6799 #define B_BE_RX_RU7_FSM_HANG_ERROR_IMR BIT(22)
6800 #define B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR BIT(21)
6801 #define B_BE_RX_CSI_FSM_HANG_ERROR_IMR BIT(20)
6802 #define B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR BIT(19)
6803 #define B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR BIT(18)
6804 #define B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR BIT(17)
6805 #define B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR BIT(16)
6806 #define B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR BIT(15)
6807 #define B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR BIT(14)
6808 #define B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR BIT(13)
6809 #define B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR BIT(12)
6810 #define B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR BIT(11)
6811 #define B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR BIT(10)
6812 #define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR BIT(9)
6813 #define B_BE_RX_CSI_ZERO_LENGTH_ERROR_IMR BIT(8)
6814 #define B_BE_PLE_DATA_OPT_FSM_HANG_IMR BIT(7)
6815 #define B_BE_PLE_RXDATA_REQUEST_BUFFER_FSM_HANG_IMR BIT(6)
6816 #define B_BE_PLE_TXRPT_REQUEST_BUFFER_FSM_HANG_IMR BIT(5)
6817 #define B_BE_PLE_WD_OPT_FSM_HANG_IMR BIT(4)
6818 #define B_BE_PLE_ENQ_FSM_HANG_IMR BIT(3)
6819 #define B_BE_RXDATA_ENQUE_ORDER_ERROR_IMR BIT(2)
6820 #define B_BE_RXSTS_ENQUE_ORDER_ERROR_IMR BIT(1)
6821 #define B_BE_RX_CSI_PKT_NUM_ERROR_IMR BIT(0)
6822 #define B_BE_RX_ERROR_FLAG_IMR_CLR (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \
6823 				    B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \
6824 				    B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \
6825 				    B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \
6826 				    B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \
6827 				    B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \
6828 				    B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \
6829 				    B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \
6830 				    B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \
6831 				    B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \
6832 				    B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \
6833 				    B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \
6834 				    B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \
6835 				    B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \
6836 				    B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \
6837 				    B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \
6838 				    B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \
6839 				    B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \
6840 				    B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \
6841 				    B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \
6842 				    B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \
6843 				    B_BE_RX_GET_NULL_PKT_ERROR_IMR)
6844 #define B_BE_RX_ERROR_FLAG_IMR_SET (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \
6845 				    B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \
6846 				    B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \
6847 				    B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \
6848 				    B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \
6849 				    B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \
6850 				    B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \
6851 				    B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \
6852 				    B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \
6853 				    B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \
6854 				    B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \
6855 				    B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \
6856 				    B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \
6857 				    B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \
6858 				    B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \
6859 				    B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \
6860 				    B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \
6861 				    B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \
6862 				    B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \
6863 				    B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \
6864 				    B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \
6865 				    B_BE_RX_GET_NULL_PKT_ERROR_IMR)
6866 
6867 #define R_BE_RX_CTRL_1 0x10C0C
6868 #define R_BE_RX_CTRL_1_C1 0x14C0C
6869 #define B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK GENMASK(30, 25)
6870 #define B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK GENMASK(23, 18)
6871 #define B_BE_RXDMA_TXRPT_PORT_ID_SW_MASK GENMASK(17, 14)
6872 #define B_BE_RXDMA_F2PCMDRPT_PORT_ID_SW_MASK GENMASK(13, 10)
6873 #define B_BE_DBG_SEL_MASK GENMASK(1, 0)
6874 #define WLCPU_RXCH2_QID 0xA
6875 
6876 #define R_BE_TX_ERROR_FLAG 0x10C6C
6877 #define R_BE_TX_ERROR_FLAG_C1 0x14C6C
6878 #define B_BE_TX_RU0_FSM_HANG_ERROR BIT(31)
6879 #define B_BE_TX_RU1_FSM_HANG_ERROR BIT(30)
6880 #define B_BE_TX_RU2_FSM_HANG_ERROR BIT(29)
6881 #define B_BE_TX_RU3_FSM_HANG_ERROR BIT(28)
6882 #define B_BE_TX_RU4_FSM_HANG_ERROR BIT(27)
6883 #define B_BE_TX_RU5_FSM_HANG_ERROR BIT(26)
6884 #define B_BE_TX_RU6_FSM_HANG_ERROR BIT(25)
6885 #define B_BE_TX_RU7_FSM_HANG_ERROR BIT(24)
6886 #define B_BE_TX_RU8_FSM_HANG_ERROR BIT(23)
6887 #define B_BE_TX_RU9_FSM_HANG_ERROR BIT(22)
6888 #define B_BE_TX_RU10_FSM_HANG_ERROR BIT(21)
6889 #define B_BE_TX_RU11_FSM_HANG_ERROR BIT(20)
6890 #define B_BE_TX_RU12_FSM_HANG_ERROR BIT(19)
6891 #define B_BE_TX_RU13_FSM_HANG_ERROR BIT(18)
6892 #define B_BE_TX_RU14_FSM_HANG_ERROR BIT(17)
6893 #define B_BE_TX_RU15_FSM_HANG_ERROR BIT(16)
6894 #define B_BE_TX_CSI_FSM_HANG_ERROR BIT(15)
6895 #define B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR BIT(14)
6896 
6897 #define R_BE_TX_ERROR_FLAG_IMR 0x10C70
6898 #define R_BE_TX_ERROR_FLAG_IMR_C1 0x14C70
6899 #define B_BE_TX_RU0_FSM_HANG_ERROR_IMR BIT(31)
6900 #define B_BE_TX_RU1_FSM_HANG_ERROR_IMR BIT(30)
6901 #define B_BE_TX_RU2_FSM_HANG_ERROR_IMR BIT(29)
6902 #define B_BE_TX_RU3_FSM_HANG_ERROR_IMR BIT(28)
6903 #define B_BE_TX_RU4_FSM_HANG_ERROR_IMR BIT(27)
6904 #define B_BE_TX_RU5_FSM_HANG_ERROR_IMR BIT(26)
6905 #define B_BE_TX_RU6_FSM_HANG_ERROR_IMR BIT(25)
6906 #define B_BE_TX_RU7_FSM_HANG_ERROR_IMR BIT(24)
6907 #define B_BE_TX_RU8_FSM_HANG_ERROR_IMR BIT(23)
6908 #define B_BE_TX_RU9_FSM_HANG_ERROR_IMR BIT(22)
6909 #define B_BE_TX_RU10_FSM_HANG_ERROR_IMR BIT(21)
6910 #define B_BE_TX_RU11_FSM_HANG_ERROR_IMR BIT(20)
6911 #define B_BE_TX_RU12_FSM_HANG_ERROR_IMR BIT(19)
6912 #define B_BE_TX_RU13_FSM_HANG_ERROR_IMR BIT(18)
6913 #define B_BE_TX_RU14_FSM_HANG_ERROR_IMR BIT(17)
6914 #define B_BE_TX_RU15_FSM_HANG_ERROR_IMR BIT(16)
6915 #define B_BE_TX_CSI_FSM_HANG_ERROR_IMR BIT(15)
6916 #define B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR BIT(14)
6917 #define B_BE_TX_ERROR_FLAG_IMR_CLR (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \
6918 				    B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \
6919 				    B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \
6920 				    B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \
6921 				    B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \
6922 				    B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \
6923 				    B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \
6924 				    B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \
6925 				    B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \
6926 				    B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \
6927 				    B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \
6928 				    B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \
6929 				    B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \
6930 				    B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \
6931 				    B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \
6932 				    B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \
6933 				    B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \
6934 				    B_BE_TX_RU0_FSM_HANG_ERROR_IMR)
6935 #define B_BE_TX_ERROR_FLAG_IMR_SET (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \
6936 				    B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \
6937 				    B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \
6938 				    B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \
6939 				    B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \
6940 				    B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \
6941 				    B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \
6942 				    B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \
6943 				    B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \
6944 				    B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \
6945 				    B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \
6946 				    B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \
6947 				    B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \
6948 				    B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \
6949 				    B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \
6950 				    B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \
6951 				    B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \
6952 				    B_BE_TX_RU0_FSM_HANG_ERROR_IMR)
6953 
6954 #define R_BE_RX_ERROR_FLAG_1 0x10C84
6955 #define R_BE_RX_ERROR_FLAG_1_C1 0x14C84
6956 #define B_BE_RX_RU8_FSM_HANG_ERROR BIT(29)
6957 #define B_BE_RX_RU9_FSM_HANG_ERROR BIT(28)
6958 #define B_BE_RX_RU10_FSM_HANG_ERROR BIT(27)
6959 #define B_BE_RX_RU11_FSM_HANG_ERROR BIT(26)
6960 #define B_BE_RX_RU12_FSM_HANG_ERROR BIT(25)
6961 #define B_BE_RX_RU13_FSM_HANG_ERROR BIT(24)
6962 #define B_BE_RX_RU14_FSM_HANG_ERROR BIT(23)
6963 #define B_BE_RX_RU15_FSM_HANG_ERROR BIT(22)
6964 #define B_BE_RX_RU8_ZERO_LENGTH_ERROR BIT(17)
6965 #define B_BE_RX_RU9_ZERO_LENGTH_ERROR BIT(16)
6966 #define B_BE_RX_RU10_ZERO_LENGTH_ERROR BIT(15)
6967 #define B_BE_RX_RU11_ZERO_LENGTH_ERROR BIT(14)
6968 #define B_BE_RX_RU12_ZERO_LENGTH_ERROR BIT(13)
6969 #define B_BE_RX_RU13_ZERO_LENGTH_ERROR BIT(12)
6970 #define B_BE_RX_RU14_ZERO_LENGTH_ERROR BIT(11)
6971 #define B_BE_RX_RU15_ZERO_LENGTH_ERROR BIT(10)
6972 
6973 #define R_BE_RX_ERROR_FLAG_IMR_1 0x10C88
6974 #define R_BE_RX_ERROR_FLAG_IMR_1_C1 0x14C88
6975 #define B_BE_RX_RU8_FSM_HANG_ERROR_IMR BIT(29)
6976 #define B_BE_RX_RU9_FSM_HANG_ERROR_IMR BIT(28)
6977 #define B_BE_RX_RU10_FSM_HANG_ERROR_IMR BIT(27)
6978 #define B_BE_RX_RU11_FSM_HANG_ERROR_IMR BIT(26)
6979 #define B_BE_RX_RU12_FSM_HANG_ERROR_IMR BIT(25)
6980 #define B_BE_RX_RU13_FSM_HANG_ERROR_IMR BIT(24)
6981 #define B_BE_RX_RU14_FSM_HANG_ERROR_IMR BIT(23)
6982 #define B_BE_RX_RU15_FSM_HANG_ERROR_IMR BIT(22)
6983 #define B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR BIT(17)
6984 #define B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR BIT(16)
6985 #define B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR BIT(15)
6986 #define B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR BIT(14)
6987 #define B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR BIT(13)
6988 #define B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR BIT(12)
6989 #define B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR BIT(11)
6990 #define B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR BIT(10)
6991 #define B_BE_TX_ERROR_FLAG_IMR_1_CLR (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \
6992 				      B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \
6993 				      B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \
6994 				      B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \
6995 				      B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \
6996 				      B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \
6997 				      B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \
6998 				      B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \
6999 				      B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \
7000 				      B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \
7001 				      B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \
7002 				      B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \
7003 				      B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \
7004 				      B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \
7005 				      B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \
7006 				      B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR)
7007 #define B_BE_TX_ERROR_FLAG_IMR_1_SET (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \
7008 				      B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \
7009 				      B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \
7010 				      B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \
7011 				      B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \
7012 				      B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \
7013 				      B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \
7014 				      B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \
7015 				      B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \
7016 				      B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \
7017 				      B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \
7018 				      B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \
7019 				      B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \
7020 				      B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \
7021 				      B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \
7022 				      B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR)
7023 
7024 #define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL 0x10E08
7025 #define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL_C1 0x14E08
7026 #define B_BE_TSFT_OFS_MASK GENMASK(31, 16)
7027 #define B_BE_STMP_THSD_MASK GENMASK(15, 8)
7028 #define B_BE_UPD_HGQMD BIT(1)
7029 #define B_BE_UPD_TIMIE BIT(0)
7030 
7031 #define R_BE_WMTX_POWER_BE_BIT_CTL 0x10E0C
7032 #define R_BE_WMTX_POWER_BE_BIT_CTL_C1 0x14E0C
7033 
7034 #define R_BE_WMTX_TCR_BE_4 0x10E2C
7035 #define R_BE_WMTX_TCR_BE_4_C1 0x14E2C
7036 #define B_BE_UL_EHT_MUMIMO_LTF_MODE BIT(30)
7037 #define B_BE_UL_HE_MUMIMO_LTF_MODE BIT(29)
7038 #define B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK GENMASK(28, 24)
7039 #define B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK GENMASK(20, 16)
7040 #define B_BE_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(12, 8)
7041 #define B_BE_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(4, 0)
7042 
7043 #define R_BE_RSP_CHK_SIG 0x11000
7044 #define R_BE_RSP_CHK_SIG_C1 0x15000
7045 #define B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30)
7046 #define B_BE_RSP_TBPPDU_CHK_PWR BIT(29)
7047 #define B_BE_RESP_PAIR_MACID_LEN_EN BIT(25)
7048 #define B_BE_RESP_TX_ABORT_TEST_EN BIT(24)
7049 #define B_BE_RESP_ER_SU_RU106_EN BIT(23)
7050 #define B_BE_RESP_ER_SU_EN BIT(22)
7051 #define B_BE_TXDATA_END_PS_OPT BIT(18)
7052 #define B_BE_CHECK_SOUNDING_SEQ BIT(17)
7053 #define B_BE_RXBA_IGNOREA2 BIT(16)
7054 #define B_BE_ACKTO_CCK_MASK GENMASK(15, 8)
7055 #define B_BE_ACKTO_MASK GENMASK(8, 0)
7056 
7057 #define R_BE_TRXPTCL_RESP_0 0x11004
7058 #define R_BE_TRXPTCL_RESP_0_C1 0x15004
7059 #define B_BE_WMAC_RESP_STBC_EN BIT(31)
7060 #define B_BE_WMAC_RXFTM_TXACK_SB BIT(30)
7061 #define B_BE_WMAC_RXFTM_TXACKBWEQ BIT(29)
7062 #define B_BE_RESP_TB_CHK_TXTIME BIT(24)
7063 #define B_BE_RSP_CHK_CCA BIT(23)
7064 #define B_BE_WMAC_LDPC_EN BIT(22)
7065 #define B_BE_WMAC_SGIEN BIT(21)
7066 #define B_BE_WMAC_SPLCPEN BIT(20)
7067 #define B_BE_RESP_EHT_MCS15_REF BIT(19)
7068 #define B_BE_RESP_EHT_MCS14_REF BIT(18)
7069 #define B_BE_WMAC_BESP_EARLY_TXBA BIT(17)
7070 #define B_BE_WMAC_MBA_DUR_FORCE BIT(16)
7071 #define B_BE_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
7072 #define WMAC_SPEC_SIFS_OFDM_1115E 0x11
7073 #define B_BE_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
7074 
7075 #define R_BE_TRXPTCL_RESP_1 0x11008
7076 #define R_BE_TRXPTCL_RESP_1_C1 0x15008
7077 #define B_BE_WMAC_RESP_SR_MODE_EN BIT(31)
7078 #define B_BE_FTM_RRSR_RATE_EN_MASK GENMASK(28, 24)
7079 #define B_BE_NESS_MASK GENMASK(23, 22)
7080 #define B_BE_WMAC_RESP_DOPPLEB_BE_EN BIT(21)
7081 #define B_BE_WMAC_RESP_DCM_EN BIT(20)
7082 #define B_BE_WMAC_CLR_ABORT_RESP_TX_CNT BIT(15)
7083 #define B_BE_WMAC_RESP_REF_RATE_SEL BIT(12)
7084 #define B_BE_WMAC_RESP_REF_RATE_MASK GENMASK(11, 0)
7085 
7086 #define R_BE_MAC_LOOPBACK 0x11020
7087 #define R_BE_MAC_LOOPBACK_C1 0x15020
7088 #define B_BE_MACLBK_DIS_GCLK BIT(30)
7089 #define B_BE_MACLBK_STS_EN BIT(29)
7090 #define B_BE_MACLBK_RDY_PERIOD_MASK GENMASK(28, 17)
7091 #define B_BE_MACLBK_PLCP_DLY_MASK GENMASK(16, 8)
7092 #define S_BE_MACLBK_PLCP_DLY_DEF 0x28
7093 #define B_BE_MACLBK_RDY_NUM_MASK GENMASK(7, 3)
7094 #define B_BE_MACLBK_EN BIT(0)
7095 
7096 #define R_BE_WMAC_NAV_CTL 0x11080
7097 #define R_BE_WMAC_NAV_CTL_C1 0x15080
7098 #define B_BE_WMAC_NAV_UPPER_EN BIT(26)
7099 #define B_BE_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
7100 #define B_BE_WMAC_PLCP_UP_NAV_EN BIT(17)
7101 #define B_BE_WMAC_TF_UP_NAV_EN BIT(16)
7102 #define B_BE_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
7103 #define NAV_25MS 0xC4
7104 #define B_BE_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
7105 
7106 #define R_BE_RXTRIG_TEST_USER_2 0x110B0
7107 #define R_BE_RXTRIG_TEST_USER_2_C1 0x150B0
7108 #define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24)
7109 #define B_BE_RXTRIG_RU26_DIS BIT(21)
7110 #define B_BE_RXTRIG_FCSCHK_EN BIT(20)
7111 #define B_BE_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
7112 #define B_BE_RXTRIG_EN BIT(16)
7113 #define B_BE_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
7114 
7115 #define R_BE_TRXPTCL_ERROR_INDICA_MASK 0x110BC
7116 #define R_BE_TRXPTCL_ERROR_INDICA_MASK_C1 0x150BC
7117 #define B_BE_WMAC_FTM_TIMEOUT_MODE BIT(30)
7118 #define B_BE_WMAC_FTM_TIMEOUT_THR_MASK GENMASK(29, 24)
7119 #define B_BE_WMAC_MODE BIT(22)
7120 #define B_BE_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
7121 #define B_BE_RMAC_BFMER BIT(9)
7122 #define B_BE_RMAC_FTM BIT(8)
7123 #define B_BE_RMAC_CSI BIT(7)
7124 #define B_BE_TMAC_MIMO_CTRL BIT(6)
7125 #define B_BE_TMAC_RXTB BIT(5)
7126 #define B_BE_TMAC_HWSIGB_GEN BIT(4)
7127 #define B_BE_TMAC_TXPLCP BIT(3)
7128 #define B_BE_TMAC_RESP BIT(2)
7129 #define B_BE_TMAC_TXCTL BIT(1)
7130 #define B_BE_TMAC_MACTX BIT(0)
7131 #define B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR (B_BE_TMAC_MACTX | \
7132 					    B_BE_TMAC_TXCTL | \
7133 					    B_BE_TMAC_RESP | \
7134 					    B_BE_TMAC_TXPLCP | \
7135 					    B_BE_TMAC_HWSIGB_GEN | \
7136 					    B_BE_TMAC_RXTB | \
7137 					    B_BE_TMAC_MIMO_CTRL | \
7138 					    B_BE_RMAC_CSI | \
7139 					    B_BE_RMAC_FTM | \
7140 					    B_BE_RMAC_BFMER)
7141 #define B_BE_TRXPTCL_ERROR_INDICA_MASK_SET (B_BE_TMAC_MACTX | \
7142 					    B_BE_TMAC_TXCTL | \
7143 					    B_BE_TMAC_RESP | \
7144 					    B_BE_TMAC_TXPLCP | \
7145 					    B_BE_TMAC_HWSIGB_GEN | \
7146 					    B_BE_TMAC_RXTB | \
7147 					    B_BE_TMAC_MIMO_CTRL | \
7148 					    B_BE_RMAC_CSI | \
7149 					    B_BE_RMAC_FTM | \
7150 					    B_BE_RMAC_BFMER)
7151 
7152 #define R_BE_TRXPTCL_ERROR_INDICA 0x110C0
7153 #define R_BE_TRXPTCL_ERROR_INDICA_C1 0x150C0
7154 #define B_BE_BFMER_ERR_FLAG BIT(9)
7155 #define B_BE_FTM_ERROR_FLAG_CLR BIT(8)
7156 #define B_BE_CSI_ERROR_FLAG_CLR BIT(7)
7157 #define B_BE_MIMOCTRL_ERROR_FLAG_CLR BIT(6)
7158 #define B_BE_RXTB_ERROR_FLAG_CLR BIT(5)
7159 #define B_BE_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
7160 #define B_BE_TXPLCP_ERROR_FLAG_CLR BIT(3)
7161 #define B_BE_RESP_ERROR_FLAG_CLR BIT(2)
7162 #define B_BE_TXCTL_ERROR_FLAG_CLR BIT(1)
7163 #define B_BE_MACTX_ERROR_FLAG_CLR BIT(0)
7164 
7165 #define R_BE_DBGSEL_TRXPTCL 0x110F4
7166 #define R_BE_DBGSEL_TRXPTCL_C1 0x150F4
7167 #define B_BE_WMAC_CHNSTS_STATE_MASK GENMASK(19, 16)
7168 #define B_BE_DBGSEL_TRIGCMD_SEL_MASK GENMASK(11, 8)
7169 #define B_BE_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
7170 
7171 #define R_BE_PHYINFO_ERR_IMR_V1 0x110F8
7172 #define R_BE_PHYINFO_ERR_IMR_V1_C1 0x150F8
7173 #define B_BE_PHYINTF_RXTB_WIDTH_MASK GENMASK(31, 30)
7174 #define B_BE_PHYINTF_RXTB_EN_PHASE_MASK GENMASK(29, 28)
7175 #define B_BE_PHYINTF_MIMO_WIDTH_MASK GENMASK(27, 26)
7176 #define B_BE_PHYINTF_MIMO_EN_PHASE_MASK GENMASK(25, 24)
7177 #define B_BE_PHYINTF_TIMEOUT_THR_V1_MASK GENMASK(21, 16)
7178 #define B_BE_CSI_ON_TIMEOUT_EN BIT(5)
7179 #define B_BE_STS_ON_TIMEOUT_EN BIT(4)
7180 #define B_BE_DATA_ON_TIMEOUT_EN BIT(3)
7181 #define B_BE_OFDM_CCA_TIMEOUT_EN BIT(2)
7182 #define B_BE_CCK_CCA_TIMEOUT_EN BIT(1)
7183 #define B_BE_PHY_TXON_TIMEOUT_EN BIT(0)
7184 #define  B_BE_PHYINFO_ERR_IMR_V1_CLR (B_BE_PHY_TXON_TIMEOUT_EN | \
7185 				      B_BE_CCK_CCA_TIMEOUT_EN | \
7186 				      B_BE_OFDM_CCA_TIMEOUT_EN | \
7187 				      B_BE_DATA_ON_TIMEOUT_EN | \
7188 				      B_BE_STS_ON_TIMEOUT_EN | \
7189 				      B_BE_CSI_ON_TIMEOUT_EN)
7190 #define B_BE_PHYINFO_ERR_IMR_V1_SET 0
7191 
7192 #define R_BE_PHYINFO_ERR_ISR 0x110FC
7193 #define R_BE_PHYINFO_ERR_ISR_C1 0x150FC
7194 #define B_BE_CSI_ON_TIMEOUT_ERR BIT(5)
7195 #define B_BE_STS_ON_TIMEOUT_ERR BIT(4)
7196 #define B_BE_DATA_ON_TIMEOUT_ERR BIT(3)
7197 #define B_BE_OFDM_CCA_TIMEOUT_ERR BIT(2)
7198 #define B_BE_CCK_CCA_TIMEOUT_ERR BIT(1)
7199 #define B_BE_PHY_TXON_TIMEOUT_ERR BIT(0)
7200 
7201 #define R_BE_BFMEE_RESP_OPTION 0x11180
7202 #define R_BE_BFMEE_RESP_OPTION_C1 0x15180
7203 #define B_BE_BFMEE_CSI_SEC_TYPE_SH 20
7204 #define B_BE_BFMEE_CSI_SEC_TYPE_MSK 0xf
7205 #define B_BE_BFMEE_BFRPT_SEG_SIZE_SH 16
7206 #define B_BE_BFMEE_BFRPT_SEG_SIZE_MSK 0x3
7207 #define B_BE_BFMEE_MIMO_EN_SEL BIT(8)
7208 #define B_BE_BFMEE_MU_BFEE_DIS BIT(7)
7209 #define B_BE_BFMEE_CHECK_RPTPOLL_MACID_DIS BIT(6)
7210 #define B_BE_BFMEE_NOCHK_BFPOLL_BMP BIT(5)
7211 #define B_BE_BFMEE_VHTBFRPT_CHK BIT(4)
7212 #define B_BE_BFMEE_EHT_NDPA_EN BIT(3)
7213 #define B_BE_BFMEE_HE_NDPA_EN BIT(2)
7214 #define B_BE_BFMEE_VHT_NDPA_EN BIT(1)
7215 #define B_BE_BFMEE_HT_NDPA_EN BIT(0)
7216 
7217 #define R_BE_TRXPTCL_RESP_CSI_CTRL_0 0x11188
7218 #define R_BE_TRXPTCL_RESP_CSI_CTRL_0_C1 0x15188
7219 #define B_BE_BFMEE_CSISEQ_SEL BIT(29)
7220 #define B_BE_BFMEE_BFPARAM_SEL BIT(28)
7221 #define B_BE_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
7222 #define B_BE_BFMEE_BF_PORT_SEL BIT(23)
7223 #define B_BE_BFMEE_USE_NSTS BIT(22)
7224 #define B_BE_BFMEE_CSI_RATE_FB_EN BIT(21)
7225 #define B_BE_BFMEE_CSI_GID_SEL BIT(20)
7226 #define B_BE_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
7227 #define B_BE_BFMEE_CSI_FORCE_RETE_EN BIT(17)
7228 #define B_BE_BFMEE_CSI_USE_NDPARATE BIT(16)
7229 #define B_BE_BFMEE_CSI_WITHHTC_EN BIT(15)
7230 #define B_BE_BFMEE_CSIINFO0_BF_EN BIT(14)
7231 #define B_BE_BFMEE_CSIINFO0_STBC_EN BIT(13)
7232 #define B_BE_BFMEE_CSIINFO0_LDPC_EN BIT(12)
7233 #define B_BE_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
7234 #define B_BE_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
7235 #define B_BE_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
7236 #define B_BE_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
7237 #define B_BE_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
7238 #define CSI_RX_BW_CFG 0x1
7239 #define R_BE_TRXPTCL_RESP_CSI_CTRL_1 0x11194
7240 #define R_BE_TRXPTCL_RESP_CSI_CTRL_1_C1 0x15194
7241 #define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24)
7242 #define CSI_RRSC_BITMAP_CFG 0x2A
7243 
7244 #define R_BE_TRXPTCL_RESP_CSI_RRSC 0x1118C
7245 #define R_BE_TRXPTCL_RESP_CSI_RRSC_C1 0x1518C
7246 #define CSI_RRSC_BMAP_BE 0x2A2AFF
7247 
7248 #define R_BE_TRXPTCL_RESP_CSI_RATE 0x11190
7249 #define R_BE_TRXPTCL_RESP_CSI_RATE_C1 0x15190
7250 #define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24)
7251 #define B_BE_BFMEE_HE_CSI_RATE_MASK GENMASK(23, 16)
7252 #define B_BE_BFMEE_VHT_CSI_RATE_MASK GENMASK(15, 8)
7253 #define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0)
7254 #define CSI_INIT_RATE_EHT 0x3
7255 
7256 #define R_BE_WMAC_ACK_BA_RESP_LEGACY 0x11200
7257 #define R_BE_WMAC_ACK_BA_RESP_LEGACY_C1 0x15200
7258 #define B_BE_ACK_BA_RESP_LEGACY_CHK_NSTR BIT(16)
7259 #define B_BE_ACK_BA_RESP_LEGACY_CHK_TX_NAV BIT(15)
7260 #define B_BE_ACK_BA_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
7261 #define B_BE_ACK_BA_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
7262 #define B_BE_ACK_BA_RESP_LEGACY_CHK_BTCCA BIT(12)
7263 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
7264 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
7265 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
7266 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
7267 #define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
7268 #define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
7269 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
7270 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
7271 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
7272 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
7273 #define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA BIT(1)
7274 #define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA BIT(0)
7275 
7276 #define R_BE_WMAC_ACK_BA_RESP_HE 0x11204
7277 #define R_BE_WMAC_ACK_BA_RESP_HE_C1 0x15204
7278 #define B_BE_ACK_BA_RESP_HE_CHK_NSTR BIT(16)
7279 #define B_BE_ACK_BA_RESP_HE_CHK_TX_NAV BIT(15)
7280 #define B_BE_ACK_BA_RESP_HE_CHK_INTRA_NAV BIT(14)
7281 #define B_BE_ACK_BA_RESP_HE_CHK_BASIC_NAV BIT(13)
7282 #define B_BE_ACK_BA_RESP_HE_CHK_BTCCA BIT(12)
7283 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA160 BIT(11)
7284 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA80 BIT(10)
7285 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA40 BIT(9)
7286 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA20 BIT(8)
7287 #define B_BE_ACK_BA_RESP_HE_CHK_EDCCA_PER20_BMP BIT(7)
7288 #define B_BE_ACK_BA_RESP_HE_CHK_CCA_PER20_BMP BIT(6)
7289 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA160 BIT(5)
7290 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA80 BIT(4)
7291 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA40 BIT(3)
7292 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA20 BIT(2)
7293 #define B_BE_ACK_BA_RESP_HE_CHK_EDCCA BIT(1)
7294 #define B_BE_ACK_BA_RESP_HE_CHK_CCA BIT(0)
7295 
7296 #define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC 0x11208
7297 #define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC_C1 0x15208
7298 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_NSTR BIT(16)
7299 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_TX_NAV BIT(15)
7300 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_INTRA_NAV BIT(14)
7301 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BASIC_NAV BIT(13)
7302 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BTCCA BIT(12)
7303 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA160 BIT(11)
7304 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA80 BIT(10)
7305 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA40 BIT(9)
7306 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA20 BIT(8)
7307 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
7308 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA_PER20_BMP BIT(6)
7309 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA160 BIT(5)
7310 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA80 BIT(4)
7311 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA40 BIT(3)
7312 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA20 BIT(2)
7313 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA BIT(1)
7314 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA BIT(0)
7315 
7316 #define R_BE_RCR 0x11400
7317 #define R_BE_RCR_C1 0x15400
7318 #define B_BE_BUSY_CHKSN BIT(15)
7319 #define B_BE_DYN_CHEN BIT(14)
7320 #define B_BE_AUTO_RST BIT(13)
7321 #define B_BE_TIMER_SEL BIT(12)
7322 #define B_BE_STOP_RX_IN BIT(11)
7323 #define B_BE_PSR_RDY_CHKDIS BIT(10)
7324 #define B_BE_DRV_INFO_SZ_MASK GENMASK(9, 8)
7325 #define B_BE_HDR_CNV_SZ_MASK GENMASK(7, 6)
7326 #define B_BE_PHY_RPT_SZ_MASK GENMASK(5, 4)
7327 #define B_BE_CH_EN BIT(0)
7328 
7329 #define R_BE_DLK_PROTECT_CTL 0x11402
7330 #define R_BE_DLK_PROTECT_CTL_C1 0x15402
7331 #define B_BE_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
7332 #define TRXCFG_RMAC_CCA_TO 32
7333 #define B_BE_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
7334 #define TRXCFG_RMAC_DATA_TO 15
7335 #define B_BE_RX_DLK_RST_FSM BIT(3)
7336 #define B_BE_RX_DLK_RST_SKIPDMA BIT(2)
7337 #define B_BE_RX_DLK_RST_EN BIT(1)
7338 #define B_BE_RX_DLK_INT_EN BIT(0)
7339 
7340 #define R_BE_PLCP_HDR_FLTR 0x11404
7341 #define R_BE_PLCP_HDR_FLTR_C1 0x15404
7342 #define B_BE_PLCP_RXFA_RESET_TYPE_MASK GENMASK(15, 12)
7343 #define B_BE_PLCP_RXFA_RESET_EN BIT(11)
7344 #define B_BE_DIS_CHK_MIN_LEN BIT(8)
7345 #define B_BE_HE_SIGB_CRC_CHK BIT(6)
7346 #define B_BE_VHT_MU_SIGB_CRC_CHK BIT(5)
7347 #define B_BE_VHT_SU_SIGB_CRC_CHK BIT(4)
7348 #define B_BE_SIGA_CRC_CHK BIT(3)
7349 #define B_BE_LSIG_PARITY_CHK_EN BIT(2)
7350 #define B_BE_CCK_SIG_CHK BIT(1)
7351 #define B_BE_CCK_CRC_CHK BIT(0)
7352 
7353 #define R_BE_RX_FLTR_OPT 0x11420
7354 #define R_BE_RX_FLTR_OPT_C1 0x15420
7355 #define B_BE_UID_FILTER_MASK GENMASK(31, 24)
7356 #define B_BE_UNSPT_TYPE BIT(22)
7357 #define B_BE_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
7358 #define B_BE_A_FTM_REQ BIT(14)
7359 #define B_BE_A_ERR_PKT BIT(13)
7360 #define B_BE_A_UNSUP_PKT BIT(12)
7361 #define B_BE_A_CRC32_ERR BIT(11)
7362 #define B_BE_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
7363 #define B_BE_A_BCN_CHK_EN BIT(7)
7364 #define B_BE_A_MC_LIST_CAM_MATCH BIT(6)
7365 #define B_BE_A_BC_CAM_MATCH BIT(5)
7366 #define B_BE_A_UC_CAM_MATCH BIT(4)
7367 #define B_BE_A_MC BIT(3)
7368 #define B_BE_A_BC BIT(2)
7369 #define B_BE_A_A1_MATCH BIT(1)
7370 #define B_BE_SNIFFER_MODE BIT(0)
7371 
7372 #define R_BE_CTRL_FLTR 0x11424
7373 #define R_BE_CTRL_FLTR_C1 0x15424
7374 #define B_BE_CTRL_STYPE_MASK GENMASK(15, 0)
7375 #define RX_FLTR_FRAME_DROP_BE 0x0000
7376 #define RX_FLTR_FRAME_ACCEPT_BE 0xFFFF
7377 
7378 #define R_BE_MGNT_FLTR 0x11428
7379 #define R_BE_MGNT_FLTR_C1 0x15428
7380 #define B_BE_MGNT_STYPE_MASK GENMASK(15, 0)
7381 
7382 #define R_BE_DATA_FLTR 0x1142C
7383 #define R_BE_DATA_FLTR_C1 0x1542C
7384 #define B_BE_DATA_STYPE_MASK GENMASK(15, 0)
7385 
7386 #define R_BE_ADDR_CAM_CTRL 0x11434
7387 #define R_BE_ADDR_CAM_CTRL_C1 0x15434
7388 #define B_BE_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
7389 #define ADDR_CAM_SERCH_RANGE  0x7f
7390 #define B_BE_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
7391 #define B_BE_ADDR_CAM_IORST BIT(10)
7392 #define B_BE_DIS_ADDR_CLK_GATED BIT(9)
7393 #define B_BE_ADDR_CAM_CLR BIT(8)
7394 #define B_BE_ADDR_CAM_A2_B0_CHK BIT(2)
7395 #define B_BE_ADDR_CAM_SRCH_PERPKT BIT(1)
7396 #define B_BE_ADDR_CAM_EN BIT(0)
7397 
7398 #define R_BE_RESPBA_CAM_CTRL 0x1143C
7399 #define R_BE_RESPBA_CAM_CTRL_C1 0x1543C
7400 #define B_BE_BACAM_SKIP_ALL_QOSNULL BIT(24)
7401 #define B_BE_BACAM_STD_SSN_SEL BIT(20)
7402 #define B_BE_BACAM_TEMP_SZ_MASK GENMASK(17, 16)
7403 #define B_BE_BACAM_RST_IDX_MASK GENMASK(15, 8)
7404 #define B_BE_BACAM_SHIFT_POLL BIT(7)
7405 #define B_BE_BACAM_IORST BIT(6)
7406 #define B_BE_BACAM_GCK_DIS BIT(5)
7407 #define B_BE_COMPL_VAL BIT(3)
7408 #define B_BE_SSN_SEL BIT(2)
7409 #define B_BE_BACAM_RST_MASK GENMASK(1, 0)
7410 #define S_BE_BACAM_RST_DONE 0
7411 #define S_BE_BACAM_RST_ENT 1
7412 #define S_BE_BACAM_RST_ALL 2
7413 
7414 #define R_BE_PPDU_STAT 0x11440
7415 #define R_BE_PPDU_STAT_C1 0x15440
7416 #define B_BE_STAT_IORST BIT(13)
7417 #define B_BE_STAT_GCKDIS BIT(12)
7418 #define B_BE_PPDU_STAT_WR_BW_MASK GENMASK(11, 10)
7419 #define B_BE_PPDU_STAT_RPT_TRIG BIT(8)
7420 #define B_BE_PPDU_STAT_RPT_DMA BIT(6)
7421 #define B_BE_PPDU_STAT_RPT_CRC32 BIT(5)
7422 #define B_BE_PPDU_STAT_RPT_ADDR BIT(4)
7423 #define B_BE_APP_PLCP_HDR_RPT BIT(3)
7424 #define B_BE_APP_RX_CNT_RPT BIT(2)
7425 #define B_BE_PPDU_MAC_INFO BIT(1)
7426 #define B_BE_PPDU_STAT_RPT_EN BIT(0)
7427 
7428 #define R_BE_RX_SR_CTRL 0x1144A
7429 #define R_BE_RX_SR_CTRL_C1 0x1544A
7430 #define B_BE_SR_OP_MODE_MASK GENMASK(5, 4)
7431 #define B_BE_SRG_CHK_EN BIT(2)
7432 #define B_BE_SR_CTRL_PLCP_EN BIT(1)
7433 #define B_BE_SR_EN BIT(0)
7434 
7435 #define R_BE_BSSID_SRC_CTRL 0x1144B
7436 #define R_BE_BSSID_SRC_CTRL_C1 0x1544B
7437 #define B_BE_BSSID_MATCH BIT(3)
7438 #define B_BE_PARTIAL_AID_MATCH BIT(2)
7439 #define B_BE_BSSCOLOR_MATCH BIT(1)
7440 #define B_BE_PLCP_SRC_EN BIT(0)
7441 
7442 #define R_BE_CSIRPT_OPTION 0x11464
7443 #define R_BE_CSIRPT_OPTION_C1 0x15464
7444 #define B_BE_CSIPRT_EHTSU_AID_EN BIT(26)
7445 #define B_BE_CSIPRT_HESU_AID_EN BIT(25)
7446 #define B_BE_CSIPRT_VHTSU_AID_EN BIT(24)
7447 
7448 #define R_BE_RX_ERR_ISR 0x114F4
7449 #define R_BE_RX_ERR_ISR_C1 0x154F4
7450 #define B_BE_RX_ERR_TRIG_ACT_TO BIT(9)
7451 #define B_BE_RX_ERR_STS_ACT_TO BIT(8)
7452 #define B_BE_RX_ERR_CSI_ACT_TO BIT(7)
7453 #define B_BE_RX_ERR_ACT_TO BIT(6)
7454 #define B_BE_CSI_DATAON_ASSERT_TO BIT(5)
7455 #define B_BE_DATAON_ASSERT_TO BIT(4)
7456 #define B_BE_CCA_ASSERT_TO BIT(3)
7457 #define B_BE_RX_ERR_DMA_TO BIT(2)
7458 #define B_BE_RX_ERR_DATA_TO BIT(1)
7459 #define B_BE_RX_ERR_CCA_TO BIT(0)
7460 
7461 #define R_BE_RX_ERR_IMR 0x114F8
7462 #define R_BE_RX_ERR_IMR_C1 0x154F8
7463 #define B_BE_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
7464 #define B_BE_RX_ERR_STS_ACT_TO_MSK BIT(8)
7465 #define B_BE_RX_ERR_CSI_ACT_TO_MSK BIT(7)
7466 #define B_BE_RX_ERR_ACT_TO_MSK BIT(6)
7467 #define B_BE_CSI_DATAON_ASSERT_TO_MSK BIT(5)
7468 #define B_BE_DATAON_ASSERT_TO_MSK BIT(4)
7469 #define B_BE_CCA_ASSERT_TO_MSK BIT(3)
7470 #define B_BE_RX_ERR_DMA_TO_MSK BIT(2)
7471 #define B_BE_RX_ERR_DATA_TO_MSK BIT(1)
7472 #define B_BE_RX_ERR_CCA_TO_MSK BIT(0)
7473 #define B_BE_RX_ERR_IMR_CLR (B_BE_RX_ERR_CCA_TO_MSK | \
7474 			     B_BE_RX_ERR_DATA_TO_MSK | \
7475 			     B_BE_RX_ERR_DMA_TO_MSK | \
7476 			     B_BE_CCA_ASSERT_TO_MSK | \
7477 			     B_BE_DATAON_ASSERT_TO_MSK | \
7478 			     B_BE_CSI_DATAON_ASSERT_TO_MSK | \
7479 			     B_BE_RX_ERR_ACT_TO_MSK | \
7480 			     B_BE_RX_ERR_CSI_ACT_TO_MSK | \
7481 			     B_BE_RX_ERR_STS_ACT_TO_MSK | \
7482 			     B_BE_RX_ERR_TRIG_ACT_TO_MSK)
7483 #define B_BE_RX_ERR_IMR_SET (B_BE_RX_ERR_ACT_TO_MSK | \
7484 			     B_BE_RX_ERR_STS_ACT_TO_MSK | \
7485 			     B_BE_RX_ERR_TRIG_ACT_TO_MSK)
7486 
7487 #define R_BE_RX_PLCP_EXT_OPTION_1 0x11514
7488 #define R_BE_RX_PLCP_EXT_OPTION_1_C1 0x15514
7489 #define B_BE_PLCP_CLOSE_RX_UNSPUUORT BIT(19)
7490 #define B_BE_PLCP_CLOSE_RX_BB_BRK BIT(18)
7491 #define B_BE_PLCP_CLOSE_RX_PSDU_PRES BIT(17)
7492 #define B_BE_PLCP_CLOSE_RX_NDP BIT(16)
7493 #define B_BE_PLCP_NSS_SRC BIT(11)
7494 #define B_BE_PLCP_DOPPLEB_BE_SRC BIT(10)
7495 #define B_BE_PLCP_STBC_SRC BIT(9)
7496 #define B_BE_PLCP_SU_PSDU_LEN_SRC BIT(8)
7497 #define B_BE_PLCP_RXSB_SRC BIT(7)
7498 #define B_BE_PLCP_BW_SRC_MASK GENMASK(6, 5)
7499 #define B_BE_PLCP_GILTF_SRC BIT(4)
7500 #define B_BE_PLCP_NSTS_SRC BIT(3)
7501 #define B_BE_PLCP_MCS_SRC BIT(2)
7502 #define B_BE_PLCP_CH20_WIDATA_SRC BIT(1)
7503 #define B_BE_PLCP_PPDU_TYPE_SRC BIT(0)
7504 
7505 #define R_BE_RESP_CSI_RESERVED_PAGE 0x11810
7506 #define R_BE_RESP_CSI_RESERVED_PAGE_C1 0x15810
7507 #define B_BE_CSI_RESERVED_PAGE_NUM_MASK GENMASK(27, 16)
7508 #define B_BE_CSI_RESERVED_START_PAGE_MASK GENMASK(11, 0)
7509 
7510 #define R_BE_RESP_IMR 0x11884
7511 #define R_BE_RESP_IMR_C1 0x15884
7512 #define B_BE_RESP_TBL_FLAG_ERR_ISR_EN BIT(17)
7513 #define B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN BIT(16)
7514 #define B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN BIT(15)
7515 #define B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN BIT(14)
7516 #define B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN BIT(13)
7517 #define B_BE_RESP_PLDID_RDY_ERR_ISR_EN BIT(12)
7518 #define B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN BIT(11)
7519 #define B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN BIT(10)
7520 #define B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN BIT(9)
7521 #define B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN BIT(8)
7522 #define B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN BIT(6)
7523 #define B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN BIT(5)
7524 #define B_BE_RESP_TXCMD_TBL_ERR_ISR_EN BIT(4)
7525 #define B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN BIT(3)
7526 #define B_BE_RESP_INITCMD_RESERVD_PAGE_ABORT_ERR_ISR_EN BIT(2)
7527 #define B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN BIT(1)
7528 #define B_BE_RESP_DMAC_PROC_ERR_ISR_EN BIT(0)
7529 #define B_BE_RESP_IMR_CLR (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \
7530 			   B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \
7531 			   B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \
7532 			   B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \
7533 			   B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \
7534 			   B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \
7535 			   B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN | \
7536 			   B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN | \
7537 			   B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN | \
7538 			   B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \
7539 			   B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \
7540 			   B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN | \
7541 			   B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN | \
7542 			   B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \
7543 			   B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN)
7544 #define B_BE_RESP_IMR_SET (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \
7545 			   B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \
7546 			   B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \
7547 			   B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \
7548 			   B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \
7549 			   B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \
7550 			   B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \
7551 			   B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \
7552 			   B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \
7553 			   B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN)
7554 
7555 #define R_BE_PWR_MODULE 0x11900
7556 #define R_BE_PWR_MODULE_C1 0x15900
7557 #define R_BE_PWR_LISTEN_PATH 0x11988
7558 #define B_BE_PWR_LISTEN_PATH_EN GENMASK(31, 28)
7559 
7560 #define R_BE_PWR_REF_CTRL 0x11A20
7561 #define B_BE_PWR_REF_CTRL_OFDM GENMASK(9, 1)
7562 #define B_BE_PWR_REF_CTRL_CCK GENMASK(18, 10)
7563 #define B_BE_PWR_OFST_LMT_DB GENMASK(27, 19)
7564 #define R_BE_PWR_OFST_LMTBF 0x11A24
7565 #define B_BE_PWR_OFST_LMTBF_DB GENMASK(8, 0)
7566 #define R_BE_PWR_FORCE_LMT 0x11A28
7567 #define B_BE_PWR_FORCE_LMT_ON BIT(6)
7568 
7569 #define R_BE_PWR_RATE_CTRL 0x11A2C
7570 #define B_BE_PWR_OFST_BYRATE_DB GENMASK(8, 0)
7571 #define B_BE_FORCE_PWR_BY_RATE_EN BIT(19)
7572 #define B_BE_FORCE_PWR_BY_RATE_VAL GENMASK(28, 20)
7573 
7574 #define R_BE_PWR_RATE_OFST_CTRL 0x11A30
7575 #define R_BE_PWR_RATE_OFST_END 0x11A38
7576 #define R_BE_PWR_RULMT_START 0x12048
7577 #define R_BE_PWR_RULMT_END 0x120e4
7578 
7579 #define R_BE_PWR_BOOST 0x11A40
7580 #define B_BE_PWR_CTRL_SEL BIT(16)
7581 #define B_BE_PWR_FORCE_RATE_ON BIT(29)
7582 #define R_BE_PWR_OFST_RULMT 0x11A44
7583 #define B_BE_PWR_OFST_RULMT_DB GENMASK(17, 9)
7584 #define B_BE_PWR_FORCE_RU_ON BIT(18)
7585 #define B_BE_PWR_FORCE_RU_ENON BIT(28)
7586 #define R_BE_PWR_FORCE_MACID 0x11A48
7587 #define B_BE_PWR_FORCE_MACID_ON BIT(9)
7588 
7589 #define R_BE_PWR_REG_CTRL 0x11A50
7590 #define B_BE_PWR_BT_EN BIT(23)
7591 
7592 #define R_BE_PWR_COEX_CTRL 0x11A54
7593 #define B_BE_PWR_BT_VAL GENMASK(8, 0)
7594 #define B_BE_PWR_FORCE_COEX_ON GENMASK(29, 27)
7595 
7596 #define R_BE_PWR_TH 0x11A78
7597 #define R_BE_PWR_RSSI_TARGET_LMT 0x11A84
7598 
7599 #define R_BE_PWR_OFST_SW 0x11AE8
7600 #define B_BE_PWR_OFST_SW_DB GENMASK(27, 24)
7601 
7602 #define R_BE_PWR_FTM 0x11B00
7603 #define R_BE_PWR_FTM_SS 0x11B04
7604 
7605 #define R_BE_PWR_BY_RATE 0x11E00
7606 #define R_BE_PWR_BY_RATE_MAX 0x11FA8
7607 #define R_BE_PWR_LMT 0x11FAC
7608 #define R_BE_PWR_LMT_MAX 0x12040
7609 #define R_BE_PWR_BY_RATE_END 0x12044
7610 #define R_BE_PWR_RU_LMT 0x12048
7611 #define R_BE_PWR_RU_LMT_MAX 0x120E4
7612 
7613 #define R_BE_C0_TXPWR_IMR 0x128E0
7614 #define R_BE_C0_TXPWR_IMR_C1 0x168E0
7615 #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0)
7616 #define B_BE_C0_TXPWR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN
7617 #define B_BE_C0_TXPWR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN
7618 
7619 #define R_BE_TXPWR_ERR_FLAG 0x128E4
7620 #define R_BE_TXPWR_ERR_IMR 0x128E0
7621 #define R_BE_TXPWR_ERR_FLAG_C1 0x158E4
7622 #define R_BE_TXPWR_ERR_IMR_C1 0x158E0
7623 
7624 #define CMAC1_START_ADDR_BE 0x14000
7625 #define CMAC1_END_ADDR_BE 0x17FFF
7626 
7627 #define RR_MOD 0x00
7628 #define RR_MOD_V1 0x10000
7629 #define RR_MOD_IQK GENMASK(19, 4)
7630 #define RR_MOD_DPK GENMASK(19, 5)
7631 #define RR_MOD_MASK GENMASK(19, 16)
7632 #define RR_MOD_DCK GENMASK(14, 10)
7633 #define RR_MOD_RGM GENMASK(13, 4)
7634 #define RR_MOD_RXB GENMASK(9, 5)
7635 #define RR_MOD_V_DOWN 0x0
7636 #define RR_MOD_V_STANDBY 0x1
7637 #define RR_TXAGC 0x10001
7638 #define RR_MOD_V_TX 0x2
7639 #define RR_MOD_V_RX 0x3
7640 #define RR_MOD_V_TXIQK 0x4
7641 #define RR_MOD_V_DPK 0x5
7642 #define RR_MOD_V_RXK1 0x6
7643 #define RR_MOD_V_RXK2 0x7
7644 #define RR_MOD_NBW GENMASK(15, 14)
7645 #define RR_MOD_M_RXG GENMASK(13, 4)
7646 #define RR_MOD_M_RXBB GENMASK(9, 5)
7647 #define RR_MOD_LO_SEL BIT(1)
7648 #define RR_MODOPT 0x01
7649 #define RR_TXG_SEL GENMASK(19, 17)
7650 #define RR_MODOPT_M_TXPWR GENMASK(5, 0)
7651 #define RR_WLSEL 0x02
7652 #define RR_WLSEL_AG GENMASK(18, 16)
7653 #define RR_RSV1 0x05
7654 #define RR_RSV1_RST BIT(0)
7655 #define RR_BBDC 0x10005
7656 #define RR_BBDC_SEL BIT(0)
7657 #define RR_DTXLOK 0x08
7658 #define RR_RSV2 0x09
7659 #define RR_LOKVB 0x0a
7660 #define RR_LOKVB_COI GENMASK(19, 14)
7661 #define RR_LOKVB_COQ GENMASK(9, 4)
7662 #define RR_TXIG 0x11
7663 #define RR_TXIG_TG GENMASK(16, 12)
7664 #define RR_TXIG_GR1 GENMASK(6, 4)
7665 #define RR_TXIG_GR0 GENMASK(1, 0)
7666 #define RR_CHTR 0x17
7667 #define RR_CHTR_MOD GENMASK(11, 10)
7668 #define RR_CHTR_TXRX GENMASK(9, 0)
7669 #define RR_CFGCH 0x18
7670 #define RR_CFGCH_V1 0x10018
7671 #define RR_CFGCH_BAND1 GENMASK(17, 16)
7672 #define CFGCH_BAND1_2G 0
7673 #define CFGCH_BAND1_5G 1
7674 #define CFGCH_BAND1_6G 3
7675 #define RR_CFGCH_POW_LCK BIT(15)
7676 #define RR_CFGCH_TRX_AH BIT(14)
7677 #define RR_CFGCH_BCN BIT(13)
7678 #define RR_CFGCH_BW2 BIT(12)
7679 #define RR_CFGCH_BAND0 GENMASK(9, 8)
7680 #define CFGCH_BAND0_2G 0
7681 #define CFGCH_BAND0_5G 1
7682 #define CFGCH_BAND0_6G 0
7683 #define RR_CFGCH_BW_V2 GENMASK(12, 10)
7684 #define CFGCH_BW_V2_20M 0
7685 #define CFGCH_BW_V2_40M 1
7686 #define CFGCH_BW_V2_80M 2
7687 #define CFGCH_BW_V2_160M 3
7688 #define CFGCH_BW_V2_320M 4
7689 #define RR_CFGCH_BW GENMASK(11, 10)
7690 #define RR_CFGCH_CH GENMASK(7, 0)
7691 #define CFGCH_BW_20M 3
7692 #define CFGCH_BW_40M 2
7693 #define CFGCH_BW_80M 1
7694 #define CFGCH_BW_160M 0
7695 #define RR_APK 0x19
7696 #define RR_APK_MOD GENMASK(5, 4)
7697 #define RR_BTC 0x1a
7698 #define RR_BTC_TXBB GENMASK(14, 12)
7699 #define RR_BTC_RXBB GENMASK(11, 10)
7700 #define RR_RCKC 0x1b
7701 #define RR_RCKC_CA GENMASK(14, 10)
7702 #define RR_RCKS 0x1c
7703 #define RR_RCKO 0x1d
7704 #define RR_RCKO_OFF GENMASK(13, 9)
7705 #define RR_RXKPLL 0x1e
7706 #define RR_RXKPLL_OFF GENMASK(5, 0)
7707 #define RR_RXKPLL_POW BIT(19)
7708 #define RR_RSV4 0x1f
7709 #define RR_RSV4_AGH GENMASK(17, 16)
7710 #define RR_RSV4_PLLCH GENMASK(9, 0)
7711 #define RR_RXK 0x20
7712 #define RR_RXK_SEL2G BIT(8)
7713 #define RR_RXK_SEL5G BIT(7)
7714 #define RR_RXK_PLLEN BIT(5)
7715 #define RR_LUTWA 0x33
7716 #define RR_LUTWA_MASK GENMASK(9, 0)
7717 #define RR_LUTWA_M1 GENMASK(7, 0)
7718 #define RR_LUTWA_M2 GENMASK(4, 0)
7719 #define RR_LUTWD1 0x3e
7720 #define RR_LUTWD0 0x3f
7721 #define RR_LUTWD0_MB GENMASK(11, 6)
7722 #define RR_LUTWD0_LB GENMASK(5, 0)
7723 #define RR_TM 0x42
7724 #define RR_TM_TRI BIT(19)
7725 #define RR_TM_VAL_V1 GENMASK(7, 0)
7726 #define RR_TM_VAL GENMASK(6, 1)
7727 #define RR_TM2 0x43
7728 #define RR_TM2_OFF GENMASK(19, 16)
7729 #define RR_TXG1 0x51
7730 #define RR_TXG1_ATT2 BIT(19)
7731 #define RR_TXG1_ATT1 BIT(11)
7732 #define RR_TXG2 0x52
7733 #define RR_TXG2_ATT0 BIT(11)
7734 #define RR_BSPAD 0x54
7735 #define RR_TXGA 0x55
7736 #define RR_TXGA_TRK_EN BIT(7)
7737 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
7738 #define RR_TXGA_LOK_EN BIT(0)
7739 #define RR_TXGA_V1 0x10055
7740 #define RR_TXGA_V1_TRK_EN BIT(7)
7741 #define RR_GAINTX 0x56
7742 #define RR_GAINTX_ALL GENMASK(15, 0)
7743 #define RR_GAINTX_PAD GENMASK(9, 5)
7744 #define RR_GAINTX_BB GENMASK(4, 0)
7745 #define RR_TXMO 0x58
7746 #define RR_TXMO_COI GENMASK(19, 15)
7747 #define RR_TXMO_COQ GENMASK(14, 10)
7748 #define RR_TXMO_FII GENMASK(9, 6)
7749 #define RR_TXMO_FIQ GENMASK(5, 2)
7750 #define RR_TXA 0x5d
7751 #define RR_TXA_TRK GENMASK(19, 14)
7752 #define RR_TXRSV 0x5c
7753 #define RR_TXRSV_GAPK BIT(19)
7754 #define RR_BIAS 0x5e
7755 #define RR_BIAS_GAPK BIT(19)
7756 #define RR_TXAC 0x5f
7757 #define RR_TXAC_IQG GENMASK(3, 0)
7758 #define RR_BIASA 0x60
7759 #define RR_BIASA_TXA GENMASK(19, 16)
7760 #define RR_BIASA_TXG GENMASK(15, 12)
7761 #define RR_BIASD_TXA_V1 GENMASK(15, 12)
7762 #define RR_BIASA_TXA_V1 GENMASK(11, 8)
7763 #define RR_BIASD_TXG_V1 GENMASK(7, 4)
7764 #define RR_BIASA_TXG_V1 GENMASK(3, 0)
7765 #define RR_BIASA_A GENMASK(2, 0)
7766 #define RR_BIASA2 0x63
7767 #define RR_BIASA2_LB GENMASK(4, 2)
7768 #define RR_TXATANK 0x64
7769 #define RR_TXATANK_LBSW2 GENMASK(17, 15)
7770 #define RR_TXATANK_LBSW GENMASK(16, 15)
7771 #define RR_TXA2 0x65
7772 #define RR_TXA2_LDO GENMASK(19, 16)
7773 #define RR_TRXIQ 0x66
7774 #define RR_RSV6 0x6d
7775 #define RR_TXVBUF 0x7c
7776 #define RR_TXVBUF_DACEN BIT(5)
7777 #define RR_TXPOW 0x7f
7778 #define RR_TXPOW_TXA BIT(8)
7779 #define RR_TXPOW_TXAS BIT(7)
7780 #define RR_TXPOW_TXG BIT(1)
7781 #define RR_RXPOW 0x80
7782 #define RR_RXPOW_IQK GENMASK(17, 16)
7783 #define RR_RXBB 0x83
7784 #define RR_RXBB_VOBUF GENMASK(15, 12)
7785 #define RR_RXBB_C2G GENMASK(16, 10)
7786 #define RR_RXBB_C2 GENMASK(11, 8)
7787 #define RR_RXBB_C1G GENMASK(9, 8)
7788 #define RR_RXBB_FATT GENMASK(7, 0)
7789 #define RR_RXBB_ATTR GENMASK(7, 4)
7790 #define RR_RXBB_ATTC GENMASK(2, 0)
7791 #define RR_RXG 0x84
7792 #define RR_RXG_IQKMOD GENMASK(19, 16)
7793 #define RR_XGLNA2 0x85
7794 #define RR_XGLNA2_SW GENMASK(1, 0)
7795 #define RR_RXAE 0x89
7796 #define RR_RXAE_IQKMOD GENMASK(3, 0)
7797 #define RR_RXA 0x8a
7798 #define RR_RXA_DPK GENMASK(9, 8)
7799 #define RR_RXA_LNA 0x8b
7800 #define RR_RXA2 0x8c
7801 #define RR_RAA2_SATT GENMASK(15, 13)
7802 #define RR_RAA2_SWATT GENMASK(15, 9)
7803 #define RR_RXA2_C1 GENMASK(12, 10)
7804 #define RR_RXA2_C2 GENMASK(9, 3)
7805 #define RR_RXA2_CC2 GENMASK(8, 7)
7806 #define RR_RXA2_IATT GENMASK(7, 4)
7807 #define RR_RXA2_HATT GENMASK(6, 0)
7808 #define RR_RXA2_ATT GENMASK(3, 0)
7809 #define RR_RXIQGEN 0x8d
7810 #define RR_RXIQGEN_ATTL GENMASK(12, 8)
7811 #define RR_RXIQGEN_ATTH GENMASK(14, 13)
7812 #define RR_RXBB2 0x8f
7813 #define RR_RXBB2_DAC_EN BIT(13)
7814 #define RR_RXBB2_CKT BIT(12)
7815 #define RR_EN_TIA_IDA GENMASK(11, 10)
7816 #define RR_RXBB2_IDAC GENMASK(11, 9)
7817 #define RR_RXBB2_EBW GENMASK(6, 5)
7818 #define RR_XALNA2 0x90
7819 #define RR_XALNA2_SW2 GENMASK(9, 8)
7820 #define RR_XALNA2_SW GENMASK(1, 0)
7821 #define RR_DCK 0x92
7822 #define RR_DCK_S1 GENMASK(19, 16)
7823 #define RR_DCK_TIA GENMASK(15, 9)
7824 #define RR_DCK_DONE GENMASK(7, 5)
7825 #define RR_DCK_FINE BIT(1)
7826 #define RR_DCK_LV BIT(0)
7827 #define RR_DCK1 0x93
7828 #define RR_DCK1_S1 GENMASK(19, 16)
7829 #define RR_DCK1_TIA GENMASK(15, 9)
7830 #define RR_DCK1_DONE BIT(5)
7831 #define RR_DCK1_CLR GENMASK(3, 0)
7832 #define RR_DCK1_SEL BIT(3)
7833 #define RR_DCK2 0x94
7834 #define RR_DCK2_CYCLE GENMASK(7, 2)
7835 #define RR_DCKC 0x95
7836 #define RR_DCKC_CHK BIT(3)
7837 #define RR_IQGEN 0x97
7838 #define RR_IQGEN_BIAS GENMASK(11, 8)
7839 #define RR_TXIQK 0x98
7840 #define RR_TXIQK_ATT2 GENMASK(15, 12)
7841 #define RR_TXIQK_ATT1 GENMASK(6, 0)
7842 #define RR_TIA 0x9e
7843 #define RR_TIA_N6 BIT(8)
7844 #define RR_MIXER 0x9f
7845 #define RR_MIXER_GN GENMASK(4, 3)
7846 #define RR_POW 0xa0
7847 #define RR_POW_SYN GENMASK(3, 2)
7848 #define RR_POW_SYN_V1 GENMASK(3, 0)
7849 #define RR_LOGEN 0xa3
7850 #define RR_LOGEN_RPT GENMASK(19, 16)
7851 #define RR_SX 0xaf
7852 #define RR_IBD 0xc9
7853 #define RR_IBD_VAL GENMASK(4, 0)
7854 #define RR_LDO 0xb1
7855 #define RR_LDO_SEL GENMASK(8, 6)
7856 #define RR_VCO 0xb2
7857 #define RR_VCO_SEL GENMASK(9, 8)
7858 #define RR_VCI 0xb3
7859 #define RR_VCI_ON BIT(7)
7860 #define RR_LPF 0xb7
7861 #define RR_LPF_BUSY BIT(8)
7862 #define RR_XTALX2 0xb8
7863 #define RR_MALSEL 0xbe
7864 #define RR_SYNFB 0xc5
7865 #define RR_SYNFB_LK BIT(15)
7866 #define RR_AACK 0xca
7867 #define RR_LCKST 0xcf
7868 #define RR_LCKST_BIN BIT(0)
7869 #define RR_LCK_TRG 0xd3
7870 #define RR_LCK_TRGSEL BIT(8)
7871 #define RR_LCK_ST BIT(4)
7872 #define RR_MMD 0xd5
7873 #define RR_MMD_RST_EN BIT(8)
7874 #define RR_MMD_RST_SYN BIT(6)
7875 #define RR_SMD 0xd6
7876 #define RR_VCO2 BIT(19)
7877 #define RR_IQKPLL 0xdc
7878 #define RR_IQKPLL_MOD GENMASK(9, 8)
7879 #define RR_SYNLUT 0xdd
7880 #define RR_SYNLUT_MOD BIT(4)
7881 #define RR_RCKD 0xde
7882 #define RR_RCKD_POW GENMASK(19, 13)
7883 #define RR_RCKD_BW BIT(2)
7884 #define RR_TXADBG 0xde
7885 #define RR_LUTDBG 0xdf
7886 #define RR_LUTDBG_TIA BIT(12)
7887 #define RR_LUTDBG_LOK BIT(2)
7888 #define RR_LUTPLL 0xec
7889 #define RR_CAL_RW BIT(19)
7890 #define RR_LUTWE2 0xee
7891 #define RR_LUTWE2_RTXBW BIT(2)
7892 #define RR_LUTWE2_DIS BIT(6)
7893 #define RR_LUTWE 0xef
7894 #define RR_LUTWE_LOK BIT(2)
7895 #define RR_RFC 0xf0
7896 #define RR_WCAL BIT(16)
7897 #define RR_RFC_CKEN BIT(1)
7898 
7899 #define R_UPD_P0 0x0000
7900 #define R_BBCLK 0x0000
7901 #define B_CLK_640M BIT(2)
7902 #define R_RSTB_WATCH_DOG 0x000C
7903 #define B_P0_RSTB_WATCH_DOG BIT(0)
7904 #define B_P1_RSTB_WATCH_DOG BIT(1)
7905 #define B_UPD_P0_EN BIT(31)
7906 #define R_EMLSR 0x0044
7907 #define B_EMLSR_PARM GENMASK(27, 12)
7908 #define R_CHK_LPS_STAT 0x0058
7909 #define B_CHK_LPS_STAT BIT(0)
7910 #define R_SPOOF_CG 0x00B4
7911 #define B_SPOOF_CG_EN BIT(17)
7912 #define R_CHINFO_SEG 0x00B4
7913 #define B_CHINFO_SEG_LEN GENMASK(2, 0)
7914 #define B_CHINFO_SEG GENMASK(16, 7)
7915 #define R_DFS_FFT_CG 0x00B8
7916 #define B_DFS_CG_EN BIT(1)
7917 #define B_DFS_FFT_EN BIT(0)
7918 #define R_CHINFO_DATA 0x00C0
7919 #define B_CHINFO_DATA_BITMAP GENMASK(22, 0)
7920 #define R_ANAPAR_PW15 0x030C
7921 #define B_ANAPAR_PW15 GENMASK(31, 24)
7922 #define B_ANAPAR_PW15_H GENMASK(27, 24)
7923 #define B_ANAPAR_PW15_H2 GENMASK(27, 26)
7924 #define R_ANAPAR 0x032C
7925 #define B_ANAPAR_15 GENMASK(31, 16)
7926 #define B_ANAPAR_EN1 BIT(31)
7927 #define B_ANAPAR_ADCCLK BIT(30)
7928 #define B_ANAPAR_FLTRST BIT(22)
7929 #define B_ANAPAR_CRXBB GENMASK(18, 16)
7930 #define B_ANAPAR_EN BIT(16)
7931 #define B_ANAPAR_14 GENMASK(15, 0)
7932 #define R_RFE_E_A2 0x0334
7933 #define R_RFE_O_SEL_A2 0x0338
7934 #define R_RFE_SEL0_A2 0x033C
7935 #define B_RFE_SEL0_MASK GENMASK(1, 0)
7936 #define R_RFE_SEL32_A2 0x0340
7937 #define R_CIRST 0x035c
7938 #define B_CIRST_SYN GENMASK(11, 10)
7939 #define R_SWSI_DATA_V1 0x0370
7940 #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
7941 #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
7942 #define B_SWSI_DATA_PATH_V1 GENMASK(30, 28)
7943 #define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31)
7944 #define R_SWSI_BIT_MASK_V1 0x0374
7945 #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
7946 #define R_SWSI_READ_ADDR_V1 0x0378
7947 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
7948 #define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8)
7949 #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
7950 #define R_BRK_R 0x0418
7951 #define B_VHTMCS_LMT GENMASK(22, 21)
7952 #define B_HTMCS_LMT GENMASK(9, 8)
7953 #define R_BRK_EHT 0x0474
7954 #define B_RXEHT_NSS_MAX GENMASK(4, 2)
7955 #define R_BRK_RXEHT 0x0478
7956 #define B_RXEHT_N_USER_MAX GENMASK(31, 24)
7957 #define B_RXEHTTB_NSS_MAX GENMASK(16, 14)
7958 #define R_EN_SND_WO_NDP 0x047c
7959 #define R_EN_SND_WO_NDP_C1 0x147c
7960 #define B_EN_SND_WO_NDP BIT(1)
7961 #define R_BRK_HE 0x0480
7962 #define B_TB_NSS_MAX GENMASK(25, 23)
7963 #define B_NSS_MAX GENMASK(16, 14)
7964 #define B_N_USR_MAX GENMASK(13, 6)
7965 #define R_RXCCA_BE1 0x0520
7966 #define B_RXCCA_BE1_DIS BIT(0)
7967 #define R_UPD_CLK_ADC 0x0700
7968 #define B_UPD_GEN_ON BIT(27)
7969 #define B_UPD_CLK_ADC_VAL GENMASK(26, 25)
7970 #define B_UPD_CLK_ADC_ON BIT(24)
7971 #define B_ENABLE_CCK BIT(5)
7972 #define R_RSTB_ASYNC 0x0704
7973 #define B_RSTB_ASYNC_BW80 GENMASK(9, 8)
7974 #define B_RSTB_ASYNC_ALL BIT(1)
7975 #define R_P0_ANT_SW 0x0728
7976 #define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
7977 #define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
7978 #define R_MAC_PIN_SEL 0x0734
7979 #define B_CH_IDX_SEG0 GENMASK(23, 16)
7980 #define R_PLCP_HISTOGRAM 0x0738
7981 #define B_STS_PARSING_TIME GENMASK(19, 16)
7982 #define B_STS_DIS_TRIG_BY_FAIL BIT(3)
7983 #define B_STS_DIS_TRIG_BY_BRK BIT(2)
7984 #define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL
7985 #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)
7986 #define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C
7987 #define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f
7988 #define R_PHY_STS_BITMAP_R2T 0x0740
7989 #define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744
7990 #define R_PHY_STS_BITMAP_OFDM_BRK 0x0748
7991 #define R_PHY_STS_BITMAP_CCK_BRK 0x074C
7992 #define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750
7993 #define R_PHY_STS_BITMAP_HE_MU 0x0754
7994 #define R_PHY_STS_BITMAP_VHT_MU 0x0758
7995 #define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C
7996 #define R_PHY_STS_BITMAP_TRIGBASE 0x0760
7997 #define R_PHY_STS_BITMAP_CCK 0x0764
7998 #define R_PHY_STS_BITMAP_LEGACY 0x0768
7999 #define R_PHY_STS_BITMAP_HT 0x076C
8000 #define R_PHY_STS_BITMAP_VHT 0x0770
8001 #define R_PHY_STS_BITMAP_HE 0x0774
8002 #define R_EDCCA_RPTREG_SEL_BE 0x078C
8003 #define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20)
8004 #define R_PMAC_GNT 0x0980
8005 #define B_PMAC_GNT_TXEN BIT(0)
8006 #define B_PMAC_GNT_RXEN BIT(16)
8007 #define B_PMAC_GNT_P1 GENMASK(20, 17)
8008 #define B_PMAC_GNT_P2 GENMASK(29, 26)
8009 #define R_PMAC_RX_CFG1 0x0988
8010 #define B_PMAC_OPT1_MSK GENMASK(11, 0)
8011 #define R_PMAC_RXMOD 0x0994
8012 #define B_PMAC_RXMOD_MSK GENMASK(7, 4)
8013 #define R_MAC_SEL 0x09A4
8014 #define B_MAC_SEL_OFDM_TRI_FILTER BIT(31)
8015 #define B_MAC_SEL GENMASK(19, 17)
8016 #define B_MAC_SEL_PWR_EN BIT(16)
8017 #define B_MAC_SEL_DPD_EN BIT(10)
8018 #define B_MAC_SEL_MOD GENMASK(4, 2)
8019 #define R_PMAC_TX_CTRL 0x09C0
8020 #define B_PMAC_TXEN_DIS BIT(0)
8021 #define R_PMAC_TX_PRD 0x09C4
8022 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
8023 #define B_PMAC_CTX_EN BIT(0)
8024 #define B_PMAC_PTX_EN BIT(4)
8025 #define R_PMAC_TX_CNT 0x09C8
8026 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
8027 #define R_P80_AT_HIGH_FREQ 0x09D8
8028 #define B_P80_AT_HIGH_FREQ BIT(26)
8029 #define R_DBCC_80P80_SEL_EVM_RPT 0x0A10
8030 #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0)
8031 #define R_CCX 0x0C00
8032 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
8033 #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)
8034 #define B_MEASUREMENT_TRIG_MSK BIT(2)
8035 #define B_CCX_TRIG_OPT_MSK BIT(1)
8036 #define B_CCX_EN_MSK BIT(0)
8037 #define R_FAHM 0x0C1C
8038 #define B_RXTD_CKEN BIT(2)
8039 #define R_IFS_COUNTER 0x0C28
8040 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
8041 #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)
8042 #define B_IFS_COUNTER_CLR_MSK BIT(13)
8043 #define B_IFS_COLLECT_EN BIT(12)
8044 #define R_IFS_T1 0x0C2C
8045 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
8046 #define B_IFS_T1_EN_MSK BIT(15)
8047 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
8048 #define R_IFS_T2 0x0C30
8049 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
8050 #define B_IFS_T2_EN_MSK BIT(15)
8051 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
8052 #define R_IFS_T3 0x0C34
8053 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
8054 #define B_IFS_T3_EN_MSK BIT(15)
8055 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
8056 #define R_IFS_T4 0x0C38
8057 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
8058 #define B_IFS_T4_EN_MSK BIT(15)
8059 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
8060 #define R_PD_CTRL 0x0C3C
8061 #define B_PD_HIT_DIS BIT(9)
8062 #define R_IOQ_IQK_DPK 0x0C60
8063 #define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0)
8064 #define B_IOQ_IQK_DPK_EN BIT(1)
8065 #define R_GNT_BT_WGT_EN 0x0C6C
8066 #define B_GNT_BT_WGT_EN BIT(21)
8067 #define R_IQK_DPK_RST 0x0C6C
8068 #define R_IQK_DPK_RST_C1 0x1C6C
8069 #define B_IQK_DPK_RST BIT(0)
8070 #define R_TX_COLLISION_T2R_ST 0x0C70
8071 #define B_TX_COLLISION_T2R_ST_M GENMASK(25, 20)
8072 #define B_TXRX_FORCE_VAL GENMASK(9, 0)
8073 #define R_TXGATING 0x0C74
8074 #define B_TXGATING_EN BIT(4)
8075 #define R_TXRFC 0x0C7C
8076 #define R_TXRFC_C1 0x1C7C
8077 #define B_TXRFC_RST GENMASK(23, 21)
8078 #define R_PD_ARBITER_OFF 0x0C80
8079 #define B_PD_ARBITER_OFF BIT(31)
8080 #define R_SNDCCA_A1 0x0C9C
8081 #define B_SNDCCA_A1_EN GENMASK(19, 12)
8082 #define R_SNDCCA_A2 0x0CA0
8083 #define B_SNDCCA_A2_VAL GENMASK(19, 12)
8084 #define R_UDP_COEEF 0x0CBC
8085 #define B_UDP_COEEF BIT(19)
8086 #define R_TX_COLLISION_T2R_ST_BE 0x0CC8
8087 #define B_TX_COLLISION_T2R_ST_BE_M GENMASK(13, 8)
8088 #define R_RXHT_MCS_LIMIT 0x0D18
8089 #define B_RXHT_MCS_LIMIT GENMASK(9, 8)
8090 #define R_RXVHT_MCS_LIMIT 0x0D18
8091 #define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
8092 #define R_P0_EN_SOUND_WO_NDP 0x0D7C
8093 #define B_P0_EN_SOUND_WO_NDP BIT(1)
8094 #define R_RXHE 0x0D80
8095 #define B_RXHETB_MAX_NSS GENMASK(25, 23)
8096 #define B_RXHE_MAX_NSS GENMASK(16, 14)
8097 #define B_RXHE_USER_MAX GENMASK(13, 6)
8098 #define R_SPOOF_ASYNC_RST 0x0D84
8099 #define B_SPOOF_ASYNC_RST BIT(15)
8100 #define R_NDP_BRK0 0xDA0
8101 #define R_NDP_BRK1 0xDA4
8102 #define B_NDP_RU_BRK BIT(0)
8103 #define R_BRK_ASYNC_RST_EN_1 0x0DC0
8104 #define R_BRK_ASYNC_RST_EN_2 0x0DC4
8105 #define R_BRK_ASYNC_RST_EN_3 0x0DC8
8106 #define R_CTLTOP 0x1008
8107 #define B_CTLTOP_ON BIT(23)
8108 #define B_CTLTOP_VAL GENMASK(15, 12)
8109 #define R_CLK_GCK 0x1008
8110 #define B_CLK_GCK GENMASK(24, 0)
8111 #define R_EDCCA_RPT_SEL_BE 0x10CC
8112 #define R_ADC_FIFO_V1 0x10FC
8113 #define B_ADC_FIFO_EN_V1 GENMASK(31, 24)
8114 #define R_S0_HW_SI_DIS 0x1200
8115 #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
8116 #define R_P0_RXCK 0x12A0
8117 #define B_P0_RXCK_ADJ GENMASK(31, 23)
8118 #define B_P0_RXCK_BW3 BIT(30)
8119 #define B_P0_TXCK_ALL GENMASK(19, 12)
8120 #define B_P0_RXCK_ON BIT(19)
8121 #define B_P0_RXCK_VAL GENMASK(18, 16)
8122 #define B_P0_TXCK_ON BIT(15)
8123 #define B_P0_TXCK_VAL GENMASK(14, 12)
8124 #define R_P0_RFMODE 0x12AC
8125 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
8126 #define B_P0_RFMODE_MUX GENMASK(11, 4)
8127 #define R_P0_RFMODE_ORI_RX 0x12AC
8128 #define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12)
8129 #define R_P0_RFMODE_FTM_RX 0x12B0
8130 #define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
8131 #define R_P0_NRBW 0x12B8
8132 #define B_P0_NRBW_DBG BIT(30)
8133 #define B_P0_NRBW_RSTB BIT(28)
8134 #define R_S0_RXDC 0x12D4
8135 #define B_S0_RXDC_I GENMASK(25, 16)
8136 #define B_S0_RXDC_Q GENMASK(31, 26)
8137 #define R_S0_RXDC2 0x12D8
8138 #define B_S0_RXDC2_SEL GENMASK(9, 8)
8139 #define B_S0_RXDC2_AVG GENMASK(7, 6)
8140 #define B_S0_RXDC2_MEN GENMASK(5, 4)
8141 #define B_S0_RXDC2_Q2 GENMASK(3, 0)
8142 #define R_CFO_COMP_SEG0_L 0x1384
8143 #define R_CFO_COMP_SEG0_H 0x1388
8144 #define R_CFO_COMP_SEG0_CTRL 0x138C
8145 #define R_DBG32_D 0x1730
8146 #define R_EDCCA_RPT_A 0x1738
8147 #define R_EDCCA_RPT_B 0x173c
8148 #define B_EDCCA_RPT_B_FB BIT(7)
8149 #define B_EDCCA_RPT_B_P20 BIT(6)
8150 #define B_EDCCA_RPT_B_S20 BIT(5)
8151 #define B_EDCCA_RPT_B_S40 BIT(4)
8152 #define B_EDCCA_RPT_B_S80 BIT(3)
8153 #define B_EDCCA_RPT_B_PATH_MASK GENMASK(2, 1)
8154 #define R_SWSI_V1 0x174C
8155 #define B_SWSI_W_BUSY_V1 BIT(24)
8156 #define B_SWSI_R_BUSY_V1 BIT(25)
8157 #define B_SWSI_R_DATA_DONE_V1 BIT(26)
8158 #define R_TX_COUNTER 0x1A40
8159 #define R_IFS_CLM_TX_CNT 0x1ACC
8160 #define R_IFS_CLM_TX_CNT_V1 0x0ECC
8161 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
8162 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
8163 #define R_IFS_CLM_CCA 0x1AD0
8164 #define R_IFS_CLM_CCA_V1 0x0ED0
8165 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
8166 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
8167 #define R_IFS_CLM_FA 0x1AD4
8168 #define R_IFS_CLM_FA_V1 0x0ED4
8169 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
8170 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
8171 #define R_IFS_HIS 0x1AD8
8172 #define R_IFS_HIS_V1 0x0ED8
8173 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
8174 #define B_IFS_T3_HIS_MSK GENMASK(23, 16)
8175 #define B_IFS_T2_HIS_MSK GENMASK(15, 8)
8176 #define B_IFS_T1_HIS_MSK GENMASK(7, 0)
8177 #define R_IFS_AVG_L 0x1ADC
8178 #define R_IFS_AVG_L_V1 0x0EDC
8179 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
8180 #define B_IFS_T1_AVG_MSK GENMASK(15, 0)
8181 #define R_IFS_AVG_H 0x1AE0
8182 #define R_IFS_AVG_H_V1 0x0EE0
8183 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
8184 #define B_IFS_T3_AVG_MSK GENMASK(15, 0)
8185 #define R_IFS_CCA_L 0x1AE4
8186 #define R_IFS_CCA_L_V1 0x0EE4
8187 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
8188 #define B_IFS_T1_CCA_MSK GENMASK(15, 0)
8189 #define R_IFS_CCA_H 0x1AE8
8190 #define R_IFS_CCA_H_V1 0x0EE8
8191 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
8192 #define B_IFS_T3_CCA_MSK GENMASK(15, 0)
8193 #define R_IFSCNT 0x1AEC
8194 #define R_IFSCNT_V1 0x0EEC
8195 #define B_IFSCNT_DONE_MSK BIT(16)
8196 #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
8197 #define R_TXAGC_TP 0x1C04
8198 #define B_TXAGC_TP GENMASK(2, 0)
8199 #define R_TSSI_THER 0x1C10
8200 #define B_TSSI_THER GENMASK(29, 24)
8201 #define R_TSSI_CWRPT 0x1C18
8202 #define B_TSSI_CWRPT_RDY BIT(16)
8203 #define B_TSSI_CWRPT GENMASK(8, 0)
8204 #define R_TXAGC_BTP 0x1CA0
8205 #define B_TXAGC_BTP GENMASK(31, 24)
8206 #define R_TXAGC_BB 0x1C60
8207 #define B_TXAGC_BB_OFT GENMASK(31, 16)
8208 #define B_TXAGC_BB GENMASK(31, 24)
8209 #define B_TXAGC_RF GENMASK(5, 0)
8210 #define R_PATH0_TXPWR 0x1C78
8211 #define B_PATH0_TXPWR GENMASK(8, 0)
8212 #define R_S0_ADDCK 0x1E00
8213 #define B_S0_ADDCK_I GENMASK(9, 0)
8214 #define B_S0_ADDCK_Q GENMASK(19, 10)
8215 #define R_TXCKEN_FORCE 0x2008
8216 #define B_TXCKEN_FORCE_ALL GENMASK(24, 0)
8217 #define R_EDCCA_RPT_SEL 0x20CC
8218 #define B_EDCCA_RPT_SEL_MSK GENMASK(2, 0)
8219 #define R_ADC_FIFO 0x20fc
8220 #define B_ADC_FIFO_RST GENMASK(31, 24)
8221 #define B_ADC_FIFO_RXK GENMASK(31, 16)
8222 #define B_ADC_FIFO_A3 BIT(28)
8223 #define B_ADC_FIFO_A2 BIT(24)
8224 #define B_ADC_FIFO_A1 BIT(20)
8225 #define B_ADC_FIFO_A0 BIT(16)
8226 #define R_TXFIR0 0x2300
8227 #define B_TXFIR_C01 GENMASK(23, 0)
8228 #define R_TXFIR2 0x2304
8229 #define B_TXFIR_C23 GENMASK(23, 0)
8230 #define R_TXFIR4 0x2308
8231 #define B_TXFIR_C45 GENMASK(23, 0)
8232 #define R_TXFIR6 0x230c
8233 #define B_TXFIR_C67 GENMASK(23, 0)
8234 #define R_TXFIR8 0x2310
8235 #define B_TXFIR_C89 GENMASK(23, 0)
8236 #define R_TXFIRA 0x2314
8237 #define B_TXFIR_CAB GENMASK(23, 0)
8238 #define R_TXFIRC 0x2318
8239 #define B_TXFIR_CCD GENMASK(23, 0)
8240 #define R_TXFIRE 0x231c
8241 #define B_TXFIR_CEF GENMASK(23, 0)
8242 #define R_11B_RX_V1 0x2320
8243 #define B_11B_RXCCA_DIS_V1 BIT(0)
8244 #define R_RPL_OFST 0x2340
8245 #define B_RPL_OFST_MASK GENMASK(14, 8)
8246 #define R_RXCCA 0x2344
8247 #define B_RXCCA_DIS BIT(31)
8248 #define R_RXCCA_V1 0x2320
8249 #define B_RXCCA_DIS_V1 BIT(0)
8250 #define R_RXSC 0x237C
8251 #define B_RXSC_EN BIT(0)
8252 #define R_RX_RPL_OFST 0x23AC
8253 #define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
8254 #define R_RXSCOBC 0x23B0
8255 #define B_RXSCOBC_TH GENMASK(18, 0)
8256 #define R_RXSCOCCK 0x23B4
8257 #define B_RXSCOCCK_TH GENMASK(18, 0)
8258 #define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410
8259 #define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14)
8260 #define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13)
8261 #define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10
8262 #define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0)
8263 #define R_AFEDAC0 0x2A5C
8264 #define B_AFEDAC0 GENMASK(31, 27)
8265 #define R_AFEDAC1 0x2A60
8266 #define B_AFEDAC1 GENMASK(2, 0)
8267 #define R_IQKDPK_HC 0x2AB8
8268 #define B_IQKDPK_HC BIT(28)
8269 #define R_HWSI_ADD0 0x2ADC
8270 #define R_HWSI_ADD1 0x2BDC
8271 #define B_HWSI_ADD_MASK GENMASK(11, 4)
8272 #define B_HWSI_ADD_CTL_MASK GENMASK(2, 0)
8273 #define B_HWSI_ADD_RD BIT(2)
8274 #define B_HWSI_ADD_POLL_MASK GENMASK(1, 0)
8275 #define B_HWSI_ADD_RUN BIT(1)
8276 #define B_HWSI_ADD_BUSY BIT(0)
8277 #define R_HWSI_DATA 0x2AE0
8278 #define B_HWSI_DATA_VAL GENMASK(27, 8)
8279 #define B_HWSI_DATA_ADDR GENMASK(7, 0)
8280 #define R_HWSI_VAL0 0x2C24
8281 #define R_HWSI_VAL1 0x2D24
8282 #define B_HWSI_VAL_RDONE BIT(31)
8283 #define B_HWSI_VAL_BUSY BIT(29)
8284 #define R_P1_EN_SOUND_WO_NDP 0x2D7C
8285 #define B_P1_EN_SOUND_WO_NDP BIT(1)
8286 #define R_EDCCA_RPT_A_BE 0x2E38
8287 #define R_EDCCA_RPT_B_BE 0x2E3C
8288 #define R_S1_HW_SI_DIS 0x3200
8289 #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
8290 #define R_P1_RXCK 0x32A0
8291 #define B_P1_RXCK_BW3 BIT(30)
8292 #define B_P1_TXCK_ALL GENMASK(19, 12)
8293 #define B_P1_RXCK_ON BIT(19)
8294 #define B_P1_RXCK_VAL GENMASK(18, 16)
8295 #define R_P1_RFMODE 0x32AC
8296 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
8297 #define B_P1_RFMODE_MUX GENMASK(11, 4)
8298 #define R_P1_RFMODE_ORI_RX 0x32AC
8299 #define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12)
8300 #define R_P1_RFMODE_FTM_RX 0x32B0
8301 #define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
8302 #define R_P1_DBGMOD 0x32B8
8303 #define B_P1_DBGMOD_ON BIT(30)
8304 #define R_S1_RXDC 0x32D4
8305 #define B_S1_RXDC_I GENMASK(25, 16)
8306 #define B_S1_RXDC_Q GENMASK(31, 26)
8307 #define R_S1_RXDC2 0x32D8
8308 #define B_S1_RXDC2_EN GENMASK(5, 4)
8309 #define B_S1_RXDC2_SEL GENMASK(9, 8)
8310 #define B_S1_RXDC2_Q2 GENMASK(3, 0)
8311 #define R_TXAGC_BB_S1 0x3C60
8312 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
8313 #define B_TXAGC_BB_S1 GENMASK(31, 24)
8314 #define R_PATH1_TXPWR 0x3C78
8315 #define B_PATH1_TXPWR GENMASK(8, 0)
8316 #define R_S1_ADDCK 0x3E00
8317 #define B_S1_ADDCK_I GENMASK(9, 0)
8318 #define B_S1_ADDCK_Q GENMASK(19, 10)
8319 #define R_OP1DB_A 0x40B0
8320 #define B_OP1DB_A GENMASK(31, 24)
8321 #define R_OP1DB1_A 0x40BC
8322 #define B_TIA10_A GENMASK(15, 0)
8323 #define B_TIA1_A GENMASK(15, 8)
8324 #define B_TIA0_A GENMASK(7, 0)
8325 #define R_BKOFF_A 0x40E0
8326 #define B_BKOFF_IBADC_A GENMASK(23, 18)
8327 #define R_BACKOFF_A 0x40E4
8328 #define B_LNA_IBADC_A GENMASK(29, 18)
8329 #define B_BACKOFF_LNA_A GENMASK(29, 24)
8330 #define B_BACKOFF_IBADC_A GENMASK(23, 18)
8331 #define R_RXBY_WBADC_A 0x40F4
8332 #define B_RXBY_WBADC_A GENMASK(14, 10)
8333 #define R_MUIC 0x40F8
8334 #define B_MUIC_EN BIT(0)
8335 #define R_BT_RXBY_WBADC_A 0x4160
8336 #define B_BT_RXBY_WBADC_A BIT(31)
8337 #define R_BT_SHARE_A 0x4164
8338 #define B_BT_SHARE_A BIT(0)
8339 #define B_BT_TRK_OFF_A BIT(1)
8340 #define B_BTG_PATH_A BIT(4)
8341 #define R_FORCE_FIR_A 0x418C
8342 #define B_FORCE_FIR_A GENMASK(1, 0)
8343 #define R_DCFO 0x4264
8344 #define B_DCFO GENMASK(7, 0)
8345 #define R_SEG0CSI 0x42AC
8346 #define R_SEG0CSI_V1 0x42B0
8347 #define B_SEG0CSI_IDX GENMASK(10, 0)
8348 #define R_SEG0CSI_EN 0x42C4
8349 #define R_SEG0CSI_EN_V1 0x42C8
8350 #define B_SEG0CSI_EN BIT(23)
8351 #define R_BSS_CLR_MAP 0x43ac
8352 #define R_BSS_CLR_MAP_V1 0x43B0
8353 #define R_BSS_CLR_MAP_V2 0x4EB0
8354 #define B_BSS_CLR_MAP_VLD0 BIT(28)
8355 #define B_BSS_CLR_MAP_TGT GENMASK(27, 22)
8356 #define B_BSS_CLR_MAP_STAID GENMASK(21, 11)
8357 #define R_CFO_TRK0 0x4404
8358 #define R_CFO_TRK1 0x440C
8359 #define B_CFO_TRK_MSK GENMASK(14, 10)
8360 #define R_T2F_GI_COMB 0x4424
8361 #define B_T2F_GI_COMB_EN BIT(2)
8362 #define R_BT_DYN_DC_EST_EN 0x441C
8363 #define R_BT_DYN_DC_EST_EN_V1 0x4420
8364 #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
8365 #define R_ASSIGN_SBD_OPT_V1 0x4440
8366 #define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
8367 #define R_ASSIGN_SBD_OPT 0x4450
8368 #define B_ASSIGN_SBD_OPT_EN BIT(24)
8369 #define R_DCFO_COMP_S0 0x448C
8370 #define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
8371 #define R_DCFO_WEIGHT 0x4490
8372 #define B_DAC_CLK_IDX BIT(31)
8373 #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
8374 #define R_DCFO_OPT 0x4494
8375 #define B_DCFO_OPT_EN BIT(29)
8376 #define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)
8377 #define R_BANDEDGE 0x4498
8378 #define B_BANDEDGE_EN BIT(30)
8379 #define R_DPD_BF 0x44a0
8380 #define B_DPD_BF_OFDM GENMASK(16, 12)
8381 #define B_DPD_BF_SCA GENMASK(6, 0)
8382 #define R_LNA_OP 0x44B0
8383 #define B_LNA6 GENMASK(31, 24)
8384 #define R_LNA_TIA 0x44BC
8385 #define B_TIA10_B GENMASK(15, 0)
8386 #define B_TIA1_B GENMASK(15, 8)
8387 #define B_TIA0_B GENMASK(7, 0)
8388 #define R_BKOFF_B 0x44E0
8389 #define B_BKOFF_IBADC_B GENMASK(23, 18)
8390 #define R_BACKOFF_B 0x44E4
8391 #define B_LNA_IBADC_B GENMASK(29, 18)
8392 #define B_BACKOFF_LNA_B GENMASK(29, 24)
8393 #define B_BACKOFF_IBADC_B GENMASK(23, 18)
8394 #define R_RXBY_WBADC_B 0x44F4
8395 #define B_RXBY_WBADC_B GENMASK(14, 10)
8396 #define R_BT_RXBY_WBADC_B 0x4560
8397 #define B_BT_RXBY_WBADC_B BIT(31)
8398 #define R_BT_SHARE_B 0x4564
8399 #define B_BT_SHARE_B BIT(0)
8400 #define B_BT_TRK_OFF_B BIT(1)
8401 #define B_BTG_PATH_B BIT(4)
8402 #define R_TXPATH_SEL 0x458C
8403 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
8404 #define R_FORCE_FIR_B 0x458C
8405 #define B_FORCE_FIR_B GENMASK(1, 0)
8406 #define R_TXPWR 0x4594
8407 #define B_TXPWR_MSK GENMASK(30, 22)
8408 #define R_TXNSS_MAP 0x45B4
8409 #define B_TXNSS_MAP_MSK GENMASK(20, 17)
8410 #define R_PCOEFF0_V1 0x45BC
8411 #define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
8412 #define R_PCOEFF2_V1 0x45CC
8413 #define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
8414 #define R_PCOEFF4_V1 0x45D0
8415 #define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
8416 #define R_PCOEFF6_V1 0x45D4
8417 #define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
8418 #define R_PCOEFF8_V1 0x45D8
8419 #define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
8420 #define R_PCOEFFA_V1 0x45C0
8421 #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
8422 #define R_PCOEFFC_V1 0x45C4
8423 #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
8424 #define R_PCOEFFE_V1 0x45C8
8425 #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
8426 #define R_PATH0_IB_PKPW 0x4628
8427 #define B_PATH0_IB_PKPW_MSK GENMASK(11, 6)
8428 #define R_PATH0_LNA_ERR1 0x462C
8429 #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
8430 #define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12)
8431 #define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6)
8432 #define R_PATH0_LNA_ERR2 0x4630
8433 #define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18)
8434 #define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12)
8435 #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
8436 #define R_PATH0_LNA_ERR3 0x4634
8437 #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
8438 #define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18)
8439 #define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6)
8440 #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
8441 #define R_PATH0_LNA_ERR4 0x4638
8442 #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
8443 #define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12)
8444 #define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6)
8445 #define R_PATH0_LNA_ERR5 0x463C
8446 #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
8447 #define R_PATH0_TIA_ERR_G0 0x4640
8448 #define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18)
8449 #define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12)
8450 #define R_PATH0_TIA_ERR_G1 0x4644
8451 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
8452 #define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6)
8453 #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
8454 #define R_PATH0_IB_PBK 0x4650
8455 #define B_PATH0_IB_PBK_MSK GENMASK(14, 10)
8456 #define R_PATH0_RXB_INIT 0x4658
8457 #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
8458 #define R_PATH0_LNA_INIT 0x4668
8459 #define R_PATH0_LNA_INIT_V1 0x472C
8460 #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
8461 #define R_PATH0_BTG 0x466C
8462 #define B_PATH0_BTG_SHEN GENMASK(18, 17)
8463 #define R_PATH0_TIA_INIT 0x4674
8464 #define B_PATH0_TIA_INIT_IDX_MSK BIT(17)
8465 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0
8466 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24
8467 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8
8468 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3 0x41C8
8469 #define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8470 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
8471 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28
8472 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC
8473 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3 0x41CC
8474 #define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8475 #define R_PATH0_RXB_INIT_V1 0x46A8
8476 #define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
8477 #define R_PATH0_G_LNA6_OP1DB_V1 0x4688
8478 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
8479 #define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694
8480 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
8481 #define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694
8482 #define B_PATH0_R_G_OFST_MASK GENMASK(23, 16)
8483 #define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
8484 #define R_CDD_EVM_CHK_EN 0x46C0
8485 #define B_CDD_EVM_CHK_EN BIT(0)
8486 #define R_PATH0_BAND_SEL_V1 0x4738
8487 #define B_PATH0_BAND_SEL_MSK_V1 BIT(17)
8488 #define B_PATH0_BAND_NRBW_EN_V1 BIT(16)
8489 #define R_PATH0_BT_SHARE_V1 0x4738
8490 #define B_PATH0_BT_SHARE_V1 BIT(19)
8491 #define R_PATH0_BTG_PATH_V1 0x4738
8492 #define B_PATH0_BTG_PATH_V1 BIT(22)
8493 #define R_P0_NBIIDX 0x469C
8494 #define B_P0_NBIIDX_VAL GENMASK(11, 0)
8495 #define B_P0_NBIIDX_NOTCH_EN BIT(12)
8496 #define R_P0_BACKOFF_IBADC_V1 0x469C
8497 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
8498 #define B_P0_NBIIDX_NOTCH_EN_V1 BIT(12)
8499 #define R_P1_MODE 0x4718
8500 #define B_P1_MODE_SEL GENMASK(31, 30)
8501 #define R_P0_AGC_CTL 0x4730
8502 #define B_P0_AGC_EN BIT(31)
8503 #define R_PATH1_LNA_INIT 0x473C
8504 #define R_PATH1_LNA_INIT_V1 0x4A80
8505 #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
8506 #define R_PATH0_TIA_INIT_V1 0x473C
8507 #define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9)
8508 #define R_PATH1_TIA_INIT 0x4748
8509 #define B_PATH1_TIA_INIT_IDX_MSK BIT(17)
8510 #define R_PATH1_BTG 0x4740
8511 #define B_PATH1_BTG_SHEN GENMASK(18, 17)
8512 #define R_PATH1_RXB_INIT 0x472C
8513 #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
8514 #define R_PATH1_G_LNA6_OP1DB_V1 0x476C
8515 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
8516 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774
8517 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8
8518 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8
8519 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3 0x45C8
8520 #define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8521 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
8522 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC
8523 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC
8524 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3 0x45CC
8525 #define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
8526 #define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
8527 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
8528 #define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778
8529 #define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
8530 #define R_PATH1_BAND_SEL_V1 0x4AA4
8531 #define B_PATH1_BAND_SEL_MSK_V1 BIT(17)
8532 #define B_PATH1_BAND_NRBW_EN_V1 BIT(16)
8533 #define R_PATH1_BT_SHARE_V1 0x4AA4
8534 #define B_PATH1_BT_SHARE_V1 BIT(19)
8535 #define R_PATH1_BTG_PATH_V1 0x4AA4
8536 #define B_PATH1_BTG_PATH_V1 BIT(22)
8537 #define R_P1_NBIIDX 0x4770
8538 #define B_P1_NBIIDX_VAL GENMASK(11, 0)
8539 #define B_P1_NBIIDX_NOTCH_EN BIT(12)
8540 #define R_PKT_CTRL 0x47D4
8541 #define B_PKT_POP_EN BIT(8)
8542 #define R_SEG0R_PD 0x481C
8543 #define R_SEG0R_PD_V1 0x4860
8544 #define R_SEG0R_PD_V2 0x6A74
8545 #define R_SEG0R_EDCCA_LVL 0x4840
8546 #define R_SEG0R_EDCCA_LVL_V1 0x4884
8547 #define B_EDCCA_LVL_MSK3 GENMASK(31, 24)
8548 #define B_EDCCA_LVL_MSK1 GENMASK(15, 8)
8549 #define B_EDCCA_LVL_MSK0 GENMASK(7, 0)
8550 #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30)
8551 #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29)
8552 #define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
8553 #define R_PWOFST 0x488C
8554 #define B_PWOFST GENMASK(21, 17)
8555 #define R_2P4G_BAND 0x4970
8556 #define B_2P4G_BAND_SEL BIT(1)
8557 #define R_FC0_BW 0x4974
8558 #define R_FC0_BW_V1 0x49C0
8559 #define B_FC0_BW_SET GENMASK(31, 30)
8560 #define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
8561 #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
8562 #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
8563 #define B_FC0_BW_INV GENMASK(6, 0)
8564 #define R_Q_MATRIX_00 0x497C
8565 #define B_Q_MATRIX_00_IMAGINARY GENMASK(15, 0)
8566 #define B_Q_MATRIX_00_REAL GENMASK(31, 16)
8567 #define R_CHBW_MOD 0x4978
8568 #define R_CHBW_MOD_V1 0x49C4
8569 #define B_BT_SHARE BIT(14)
8570 #define B_CHBW_MOD_SBW GENMASK(13, 12)
8571 #define B_CHBW_MOD_PRICH GENMASK(11, 8)
8572 #define B_ANT_RX_SEG0 GENMASK(3, 0)
8573 #define R_Q_MATRIX_11 0x4988
8574 #define B_Q_MATRIX_11_IMAGINARY GENMASK(15, 0)
8575 #define B_Q_MATRIX_11_REAL GENMASK(31, 16)
8576 #define R_CUSTOMIZE_Q_MATRIX 0x498C
8577 #define B_CUSTOMIZE_Q_MATRIX_EN BIT(0)
8578 #define R_P0_RPL1 0x49B0
8579 #define B_P0_RPL1_41_MASK GENMASK(31, 24)
8580 #define B_P0_RPL1_40_MASK GENMASK(23, 16)
8581 #define B_P0_RPL1_20_MASK GENMASK(15, 8)
8582 #define B_P0_RPL1_MASK (B_P0_RPL1_41_MASK | B_P0_RPL1_40_MASK | B_P0_RPL1_20_MASK)
8583 #define B_P0_RPL1_SHIFT 8
8584 #define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
8585 #define R_P0_RPL2 0x49B4
8586 #define B_P0_RTL2_8A_MASK GENMASK(31, 24)
8587 #define B_P0_RTL2_81_MASK GENMASK(23, 16)
8588 #define B_P0_RTL2_80_MASK GENMASK(15, 8)
8589 #define B_P0_RTL2_42_MASK GENMASK(7, 0)
8590 #define R_P0_RPL3 0x49B8
8591 #define B_P0_RTL3_89_MASK GENMASK(31, 24)
8592 #define B_P0_RTL3_84_MASK GENMASK(23, 16)
8593 #define B_P0_RTL3_83_MASK GENMASK(15, 8)
8594 #define B_P0_RTL3_82_MASK GENMASK(7, 0)
8595 #define R_PD_BOOST_EN 0x49E8
8596 #define B_PD_BOOST_EN BIT(7)
8597 #define R_P1_BACKOFF_IBADC_V1 0x49F0
8598 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
8599 #define R_P1_RPL1 0x4A00
8600 #define R_P1_RPL2 0x4A04
8601 #define R_P1_RPL3 0x4A08
8602 #define R_BK_FC0_INV_V1 0x4A1C
8603 #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
8604 #define R_CCK_FC0_INV_V1 0x4A20
8605 #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
8606 #define R_PATH1_RXB_INIT_V1 0x4A5C
8607 #define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
8608 #define R_P1_AGC_CTL 0x4A9C
8609 #define B_P1_AGC_EN BIT(31)
8610 #define R_PATH1_TIA_INIT_V1 0x4AA8
8611 #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
8612 #define R_P0_AGC_RSVD 0x4ACC
8613 #define R_PATH0_RXBB_V1 0x4AD4
8614 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
8615 #define R_P1_AGC_RSVD 0x4AD8
8616 #define R_PATH1_RXBB_V1 0x4AE0
8617 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
8618 #define R_PATH0_BT_BACKOFF_V1 0x4AE4
8619 #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
8620 #define R_PATH1_BT_BACKOFF_V1 0x4AEC
8621 #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
8622 #define R_DCFO_COMP_S0_V2 0x4B20
8623 #define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0)
8624 #define R_PATH0_TX_CFR 0x4B30
8625 #define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10)
8626 #define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)
8627 #define R_PATH0_TX_POLAR_CLIPPING 0x4B3C
8628 #define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16)
8629 #define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12)
8630 #define R_PATH0_FRC_FIR_TYPE_V1 0x4C00
8631 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
8632 #define R_PATH0_NOTCH 0x4C14
8633 #define B_PATH0_NOTCH_EN BIT(12)
8634 #define B_PATH0_NOTCH_VAL GENMASK(11, 0)
8635 #define R_PATH0_NOTCH2 0x4C20
8636 #define B_PATH0_NOTCH2_EN BIT(12)
8637 #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
8638 #define R_PATH0_5MDET 0x4C4C
8639 #define R_PATH0_5MDET_V1 0x46F8
8640 #define B_PATH0_5MDET_EN BIT(12)
8641 #define B_PATH0_5MDET_SB2 BIT(8)
8642 #define B_PATH0_5MDET_SB0 BIT(6)
8643 #define B_PATH0_5MDET_TH GENMASK(5, 0)
8644 #define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4
8645 #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
8646 #define R_PATH1_NOTCH 0x4CD8
8647 #define B_PATH1_NOTCH_EN BIT(12)
8648 #define B_PATH1_NOTCH_VAL GENMASK(11, 0)
8649 #define R_PATH1_NOTCH2 0x4CE4
8650 #define B_PATH1_NOTCH2_EN BIT(12)
8651 #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
8652 #define R_PATH1_5MDET 0x4D10
8653 #define R_PATH1_5MDET_V1 0x47B8
8654 #define B_PATH1_5MDET_EN BIT(12)
8655 #define B_PATH1_5MDET_SB2 BIT(8)
8656 #define B_PATH1_5MDET_SB0 BIT(6)
8657 #define B_PATH1_5MDET_TH GENMASK(5, 0)
8658 #define R_S0S1_CSI_WGT 0x4D34
8659 #define B_S0S1_CSI_WGT_EN BIT(0)
8660 #define B_S0S1_CSI_WGT_TONE_IDX GENMASK(31, 20)
8661 #define R_CHINFO_ELM_SRC 0x4D84
8662 #define B_CHINFO_ELM_BITMAP GENMASK(22, 0)
8663 #define B_CHINFO_SRC GENMASK(31, 30)
8664 #define R_CHINFO_TYPE_SCAL 0x4D88
8665 #define B_CHINFO_TYPE GENMASK(2, 1)
8666 #define B_CHINFO_SCAL BIT(8)
8667 #define R_RPL_BIAS_COMP 0x4DF0
8668 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
8669 #define R_RPL_PATHAB 0x4E0C
8670 #define B_RPL_PATHB_MASK GENMASK(23, 16)
8671 #define B_RPL_PATHA_MASK GENMASK(15, 8)
8672 #define R_RSSI_M_PATHAB 0x4E2C
8673 #define B_RSSI_M_PATHB_MASK GENMASK(15, 8)
8674 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
8675 #define R_FC0_V1 0x4E30
8676 #define B_FC0_MSK_V1 GENMASK(12, 0)
8677 #define R_RX_BW40_2XFFT_EN_V1 0x4E30
8678 #define B_RX_BW40_2XFFT_EN_MSK_V1 BIT(26)
8679 #define R_DCFO_COMP_S0_V1 0x4A40
8680 #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
8681 #define R_BMODE_PDTH_V1 0x4B64
8682 #define R_BMODE_PDTH_V2 0x6708
8683 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
8684 #define R_BMODE_PDTH_EN_V1 0x4B74
8685 #define R_BMODE_PDTH_EN_V2 0x6718
8686 #define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30)
8687 #define R_BSS_CLR_VLD_V2 0x4EBC
8688 #define B_BSS_CLR_VLD0_V2 BIT(2)
8689 #define R_CFO_COMP_SEG1_L 0x5384
8690 #define R_CFO_COMP_SEG1_H 0x5388
8691 #define R_CFO_COMP_SEG1_CTRL 0x538C
8692 #define B_CFO_COMP_VALID_BIT BIT(29)
8693 #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
8694 #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
8695 #define R_TSSI_PA_K1 0x5600
8696 #define R_TSSI_PA_K2 0x5604
8697 #define R_P0_TSSI_ALIM1 0x5630
8698 #define B_P0_TSSI_ALIM1 GENMASK(29, 0)
8699 #define B_P0_TSSI_ALIM11 GENMASK(29, 20)
8700 #define B_P0_TSSI_ALIM12 GENMASK(19, 10)
8701 #define B_P0_TSSI_ALIM13 GENMASK(9, 0)
8702 #define R_P0_TSSI_ALIM3 0x5634
8703 #define B_P0_TSSI_ALIM31 GENMASK(9, 0)
8704 #define R_TSSI_PA_K5 0x5638
8705 #define R_P0_TSSI_ALIM2 0x563c
8706 #define B_P0_TSSI_ALIM2 GENMASK(29, 0)
8707 #define R_P0_TSSI_ALIM4 0x5640
8708 #define R_TSSI_PA_K8 0x5644
8709 #define R_P0_TSSI_ADC_CLK 0x566c
8710 #define B_P0_TSSI_ADC_CLK GENMASK(17, 16)
8711 #define R_UPD_CLK 0x5670
8712 #define B_DAC_VAL BIT(31)
8713 #define B_ACK_VAL GENMASK(30, 29)
8714 #define B_DPD_DIS BIT(14)
8715 #define B_DPD_GDIS BIT(13)
8716 #define B_IQK_RFC_ON BIT(1)
8717 #define R_TXPWRB 0x56CC
8718 #define B_TXPWRB_ON BIT(28)
8719 #define B_TXPWRB_VAL GENMASK(27, 19)
8720 #define R_DPD_OFT_EN 0x5800
8721 #define B_DPD_OFT_EN BIT(28)
8722 #define B_DPD_TSSI_CW GENMASK(26, 18)
8723 #define B_DPD_PWR_CW GENMASK(17, 9)
8724 #define B_DPD_REF GENMASK(8, 0)
8725 #define R_P0_TSSIC 0x5814
8726 #define B_P0_TSSIC_BYPASS BIT(11)
8727 #define R_DPD_OFT_ADDR 0x5804
8728 #define B_DPD_OFT_ADDR GENMASK(31, 27)
8729 #define R_TXPWRB_H 0x580c
8730 #define B_TXPWRB_RDY BIT(15)
8731 #define R_P0_TMETER 0x5810
8732 #define B_P0_TMETER GENMASK(15, 10)
8733 #define B_P0_TMETER_DIS BIT(16)
8734 #define B_P0_TMETER_TRK BIT(24)
8735 #define R_P0_ADCFF_EN 0x58C8
8736 #define B_P0_ADCFF_EN BIT(24)
8737 #define R_P1_TSSIC 0x7814
8738 #define B_P1_TSSIC_BYPASS BIT(11)
8739 #define R_P0_TSSI_TRK 0x5818
8740 #define B_P0_TSSI_TRK_EN BIT(30)
8741 #define B_P0_TSSI_RFC GENMASK(28, 27)
8742 #define B_P0_TSSI_OFT_EN BIT(28)
8743 #define B_P0_TSSI_OFT GENMASK(7, 0)
8744 #define R_P0_TSSI_AVG 0x5820
8745 #define B_P0_TSSI_EN BIT(31)
8746 #define B_P0_TSSI_AVG GENMASK(15, 12)
8747 #define R_P0_RFCTM 0x5864
8748 #define B_P0_CLKG_FORCE GENMASK(31, 30)
8749 #define B_P0_RFCTM_EN BIT(29)
8750 #define B_P0_GOT_TXRX GENMASK(28, 27)
8751 #define B_P0_RFCTM_VAL GENMASK(25, 20)
8752 #define R_P0_RFCTM_RDY BIT(26)
8753 #define R_P0_TRSW 0x5868
8754 #define B_P0_BT_FORCE_ANTIDX_EN BIT(12)
8755 #define B_P0_TRSW_X BIT(2)
8756 #define B_P0_TRSW_A BIT(1)
8757 #define B_P0_TX_ANT_SEL BIT(1)
8758 #define B_P0_TRSW_B BIT(0)
8759 #define B_P0_ANT_TRAIN_EN BIT(0)
8760 #define B_P0_TRSW_SO_A2 GENMASK(7, 5)
8761 #define R_P0_ANTSEL 0x586C
8762 #define B_P0_ANTSEL_SW_5G BIT(25)
8763 #define B_P0_ANTSEL_SW_2G BIT(23)
8764 #define B_P0_ANTSEL_BTG_TRX BIT(21)
8765 #define B_P0_ANTSEL_CGCS_CTRL BIT(17)
8766 #define B_P0_ANTSEL_HW_CTRL BIT(16)
8767 #define B_P0_ANTSEL_TX_ORI GENMASK(15, 12)
8768 #define B_P0_ANTSEL_RX_ALT GENMASK(11, 8)
8769 #define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)
8770 #define R_RFSW_CTRL_ANT0_BASE 0x5870
8771 #define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)
8772 #define R_RFE_SEL0_BASE 0x5880
8773 #define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)
8774 #define R_RFE_SEL32_BASE 0x5884
8775 #define RFE_SEL0_SRC_ANTSEL_0 8
8776 #define R_RFE_INV0 0x5890
8777 #define R_P0_RFM 0x5894
8778 #define B_P0_RFM_DIS_WL BIT(7)
8779 #define B_P0_RFM_TX_OPT BIT(6)
8780 #define B_P0_RFM_BT_EN BIT(5)
8781 #define B_P0_RFM_OUT GENMASK(4, 0)
8782 #define R_P0_PATH_RST 0x58AC
8783 #define B_P0_PATH_RST BIT(27)
8784 #define R_P0_TXDPD 0x58D4
8785 #define B_P0_TXDPD GENMASK(31, 28)
8786 #define R_P0_TXPW_RSTB 0x58DC
8787 #define B_P0_TXPW_RSTB_MANON BIT(30)
8788 #define B_P0_TXPW_RSTB_TSSI BIT(31)
8789 #define R_P0_TSSI_MV_AVG 0x58E4
8790 #define B_P0_TXPW_RSTB GENMASK(28, 27)
8791 #define B_P0_TSSI_MV_MIX GENMASK(19, 11)
8792 #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
8793 #define B_P0_TSSI_MV_CLR BIT(14)
8794 #define R_TXGAIN_SCALE 0x58F0
8795 #define B_TXGAIN_SCALE_EN BIT(19)
8796 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
8797 #define R_P0_DAC_COMP_POST_DPD_EN 0x58F8
8798 #define B_P0_DAC_COMP_POST_DPD_EN BIT(31)
8799 #define R_P0_TSSI_BASE 0x5C00
8800 #define R_S0_DACKI 0x5E00
8801 #define B_S0_DACKI_AR GENMASK(31, 28)
8802 #define B_S0_DACKI_EN BIT(3)
8803 #define R_S0_DACKI2 0x5E30
8804 #define B_S0_DACKI2_K GENMASK(21, 12)
8805 #define R_S0_DACKI7 0x5E44
8806 #define B_S0_DACKI7_K GENMASK(15, 8)
8807 #define R_S0_DACKI8 0x5E48
8808 #define B_S0_DACKI8_K GENMASK(15, 8)
8809 #define R_S0_DACKQ 0x5E50
8810 #define B_S0_DACKQ_AR GENMASK(31, 28)
8811 #define B_S0_DACKQ_EN BIT(3)
8812 #define R_S0_DACKQ2 0x5E80
8813 #define B_S0_DACKQ2_K GENMASK(21, 12)
8814 #define R_S0_DACKQ7 0x5E94
8815 #define B_S0_DACKQ7_K GENMASK(15, 8)
8816 #define R_S0_DACKQ8 0x5E98
8817 #define B_S0_DACKQ8_K GENMASK(15, 8)
8818 #define R_DCFO_WEIGHT_V1 0x6244
8819 #define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28)
8820 #define R_DAC_CLK 0x625C
8821 #define B_DAC_CLK GENMASK(31, 30)
8822 #define R_DCFO_OPT_V1 0x6260
8823 #define B_DCFO_OPT_EN_V1 BIT(17)
8824 #define R_TXFCTR 0x627C
8825 #define B_TXFCTR_THD GENMASK(19, 10)
8826 #define R_TXSCALE 0x6284
8827 #define B_TXFCTR_EN BIT(19)
8828 #define R_PCOEFF01 0x6684
8829 #define B_PCOEFF01 GENMASK(23, 0)
8830 #define R_PCOEFF23 0x6688
8831 #define B_PCOEFF23 GENMASK(23, 0)
8832 #define R_PCOEFF45 0x668c
8833 #define B_PCOEFF45 GENMASK(23, 0)
8834 #define R_PCOEFF67 0x6690
8835 #define B_PCOEFF67 GENMASK(23, 0)
8836 #define R_PCOEFF89 0x6694
8837 #define B_PCOEFF89 GENMASK(23, 0)
8838 #define R_PCOEFFAB 0x6698
8839 #define B_PCOEFFAB GENMASK(23, 0)
8840 #define R_PCOEFFCD 0x669c
8841 #define B_PCOEFFCD GENMASK(23, 0)
8842 #define R_PCOEFFEF 0x66a0
8843 #define B_PCOEFFEF GENMASK(23, 0)
8844 #define R_MGAIN_BIAS 0x672c
8845 #define B_MGAIN_BIAS_BW20 GENMASK(3, 0)
8846 #define B_MGAIN_BIAS_BW40 GENMASK(7, 4)
8847 #define R_CCK_RPL_OFST 0x6750
8848 #define B_CCK_RPL_OFST GENMASK(7, 0)
8849 #define R_BK_FC0INV 0x6758
8850 #define B_BK_FC0INV GENMASK(18, 0)
8851 #define R_CCK_FC0INV 0x675c
8852 #define B_CCK_FC0INV GENMASK(18, 0)
8853 #define R_SEG0R_EDCCA_LVL_BE 0x69EC
8854 #define R_SEG0R_PPDU_LVL_BE 0x69F0
8855 #define R_SEGSND 0x6A14
8856 #define B_SEGSND_EN BIT(31)
8857 #define R_DBCC 0x6B48
8858 #define B_DBCC_EN BIT(0)
8859 #define R_FC0 0x6B4C
8860 #define B_BW40_2XFFT BIT(31)
8861 #define B_FC0 GENMASK(12, 0)
8862 #define R_FC0INV_SBW 0x6B50
8863 #define B_SMALLBW GENMASK(31, 30)
8864 #define B_RX_BT_SG0 GENMASK(25, 22)
8865 #define B_RX_1RCCA GENMASK(17, 14)
8866 #define B_FC0_INV GENMASK(6, 0)
8867 #define R_ANT_CHBW 0x6B54
8868 #define B_ANT_BT_SHARE BIT(16)
8869 #define B_CHBW_BW GENMASK(14, 12)
8870 #define B_CHBW_PRICH GENMASK(11, 8)
8871 #define B_ANT_RX_SG0 GENMASK(3, 0)
8872 #define R_SLOPE 0x6B6C
8873 #define B_EHT_RATE_TH GENMASK(31, 28)
8874 #define B_SLOPE_B GENMASK(27, 14)
8875 #define B_SLOPE_A GENMASK(13, 0)
8876 #define R_SC_CORNER 0x6B70
8877 #define B_SC_CORNER GENMASK(10, 0)
8878 #define R_MAG_A 0x6BF4
8879 #define B_MGA_AEND GENMASK(31, 24)
8880 #define R_MAG_AB 0x6BF8
8881 #define B_BY_SLOPE GENMASK(31, 24)
8882 #define B_MAG_AB GENMASK(23, 0)
8883 #define R_BEDGE 0x6BFC
8884 #define B_EHT_MCS14 BIT(31)
8885 #define B_HE_RATE_TH GENMASK(30, 27)
8886 #define R_BEDGE2 0x6C00
8887 #define B_EHT_MCS15 BIT(31)
8888 #define B_HT_VHT_TH GENMASK(11, 0)
8889 #define R_BEDGE3 0x6C04
8890 #define B_TB_EN BIT(23)
8891 #define B_HEMU_EN BIT(21)
8892 #define B_HEERSU_EN BIT(19)
8893 #define B_EHTTB_EN BIT(15)
8894 #define B_BEDGE_CFG GENMASK(1, 0)
8895 #define R_SU_PUNC 0x6C08
8896 #define B_SU_PUNC_EN BIT(1)
8897 #define R_BEDGE5 0x6C10
8898 #define B_HWGEN_EN BIT(25)
8899 #define B_PWROFST_COMP BIT(20)
8900 #define R_RPL_BIAS_COMP1 0x6DF0
8901 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
8902 #define R_DBCC_FA 0x703C
8903 #define B_DBCC_FA BIT(12)
8904 #define R_P1_TSSI_ALIM1 0x7630
8905 #define B_P1_TSSI_ALIM1 GENMASK(29, 0)
8906 #define B_P1_TSSI_ALIM11 GENMASK(29, 20)
8907 #define B_P1_TSSI_ALIM12 GENMASK(19, 10)
8908 #define B_P1_TSSI_ALIM13 GENMASK(9, 0)
8909 #define R_P1_TSSI_ALIM3 0x7634
8910 #define B_P1_TSSI_ALIM31 GENMASK(9, 0)
8911 #define R_P1_TSSI_ALIM2 0x763c
8912 #define B_P1_TSSI_ALIM2 GENMASK(29, 0)
8913 #define R_P1_TSSI_ADC_CLK 0x766c
8914 #define B_P1_TSSI_ADC_CLK GENMASK(17, 16)
8915 #define R_P1_TXAGC_TH 0x7800
8916 #define B_P1_TXAGC_MAXMIN GENMASK(15, 0)
8917 #define R_P1_TXPW_FORCE 0x780C
8918 #define B_P1_TXPW_RDY BIT(15)
8919 #define R_P1_TSSIC 0x7814
8920 #define B_P1_TSSIC_BYPASS BIT(11)
8921 #define R_P1_TMETER 0x7810
8922 #define B_P1_TMETER GENMASK(15, 10)
8923 #define B_P1_TMETER_DIS BIT(16)
8924 #define B_P1_TMETER_TRK BIT(24)
8925 #define R_P1_TSSI_TRK 0x7818
8926 #define B_P1_TSSI_TRK_EN BIT(30)
8927 #define B_P1_TSSI_RFC GENMASK(28, 27)
8928 #define B_P1_TSSI_OFT_EN BIT(28)
8929 #define B_P1_TSSI_OFT GENMASK(7, 0)
8930 #define R_P1_TSSI_AVG 0x7820
8931 #define B_P1_TSSI_EN BIT(31)
8932 #define B_P1_TSSI_AVG GENMASK(15, 12)
8933 #define R_P1_RFCTM 0x7864
8934 #define B_P1_CLKG_FORCE GENMASK(31, 30)
8935 #define B_P1_GOT_TXRX GENMASK(28, 27)
8936 #define R_P1_RFCTM_RDY BIT(26)
8937 #define B_P1_RFCTM_VAL GENMASK(25, 20)
8938 #define B_P1_RFCTM_DEL GENMASK(19, 11)
8939 #define R_P1_PATH_RST 0x78AC
8940 #define B_P1_PATH_RST BIT(27)
8941 #define R_P1_ADCFF_EN 0x78C8
8942 #define B_P1_ADCFF_EN BIT(24)
8943 #define R_P1_TXPW_RSTB 0x78DC
8944 #define B_P1_TXPW_RSTB_MANON BIT(30)
8945 #define B_P1_TXPW_RSTB_TSSI BIT(31)
8946 #define R_P1_TSSI_MV_AVG 0x78E4
8947 #define B_P1_TXPW_RSTB GENMASK(28, 27)
8948 #define B_P1_TSSI_MV_MIX GENMASK(19, 11)
8949 #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
8950 #define B_P1_TSSI_MV_CLR BIT(14)
8951 #define R_P1_DAC_COMP_POST_DPD_EN 0x78F8
8952 #define B_P1_DAC_COMP_POST_DPD_EN BIT(31)
8953 #define R_TSSI_THOF 0x7C00
8954 #define R_S1_DACKI 0x7E00
8955 #define B_S1_DACKI_AR GENMASK(31, 28)
8956 #define B_S1_DACKI_EN BIT(3)
8957 #define R_S1_DACKI2 0x7E30
8958 #define B_S1_DACKI2_K GENMASK(21, 12)
8959 #define R_S1_DACKI7 0x7E44
8960 #define B_S1_DACKI_K GENMASK(15, 8)
8961 #define R_S1_DACKI8 0x7E48
8962 #define B_S1_DACKI8_K GENMASK(15, 8)
8963 #define R_S1_DACKQ 0x7E50
8964 #define B_S1_DACKQ_AR GENMASK(31, 28)
8965 #define B_S1_DACKQ_EN BIT(3)
8966 #define R_S1_DACKQ2 0x7E80
8967 #define B_S1_DACKQ2_K GENMASK(21, 12)
8968 #define R_S1_DACKQ7 0x7E94
8969 #define B_S1_DACKQ7_K GENMASK(15, 8)
8970 #define R_S1_DACKQ8 0x7E98
8971 #define B_S1_DACKQ8_K GENMASK(15, 8)
8972 #define R_NCTL_CFG 0x8000
8973 #define B_NCTL_CFG_SPAGE GENMASK(2, 1)
8974 #define R_NCTL_RPT 0x8008
8975 #define B_NCTL_RPT_FLG BIT(26)
8976 #define R_NCTL_N1 0x8010
8977 #define B_NCTL_N1_CIP GENMASK(7, 0)
8978 #define R_NCTL_N2 0x8014
8979 #define R_IQK_COM 0x8018
8980 #define R_IQK_DIF 0x801C
8981 #define B_IQK_DIF_TRX GENMASK(1, 0)
8982 #define R_IQK_DIF1 0x8020
8983 #define B_IQK_DIF1_TXPI GENMASK(19, 0)
8984 #define R_IQK_DIF2 0x8024
8985 #define B_IQK_DIF2_RXPI GENMASK(19, 0)
8986 #define R_IQK_DIF4 0x802C
8987 #define B_IQK_DIF4_RXT GENMASK(27, 16)
8988 #define B_IQK_DIF4_TXT GENMASK(11, 0)
8989 #define IQK_DF4_TXT_8_25MHZ 0x021
8990 #define R_IQK_CFG 0x8034
8991 #define B_IQK_CFG_SET GENMASK(5, 4)
8992 #define R_IQK_RXA 0x8044
8993 #define B_IQK_RXAGC GENMASK(15, 13)
8994 #define R_TPG_SEL 0x8068
8995 #define R_TPG_MOD 0x806C
8996 #define B_TPG_MOD_F GENMASK(2, 1)
8997 #define R_MDPK_SYNC 0x8070
8998 #define B_MDPK_SYNC_SEL BIT(31)
8999 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
9000 #define B_MDPK_SYNC_DMAN GENMASK(30, 28)
9001 #define R_MDPK_RX_DCK 0x8074
9002 #define B_MDPK_RX_DCK_EN BIT(31)
9003 #define R_KIP_MOD 0x8078
9004 #define B_KIP_MOD GENMASK(19, 0)
9005 #define R_NCTL_RW 0x8080
9006 #define R_KIP_SYSCFG 0x8088
9007 #define R_KIP_CLK 0x808C
9008 #define R_DPK_IDL 0x809C
9009 #define B_DPK_IDL_SEL GENMASK(10, 9)
9010 #define B_DPK_IDL BIT(8)
9011 #define R_LDL_NORM 0x80A0
9012 #define B_LDL_NORM_MA BIT(16)
9013 #define B_LDL_NORM_PN GENMASK(12, 8)
9014 #define B_LDL_NORM_OP GENMASK(1, 0)
9015 #define R_DPK_CTL 0x80B0
9016 #define B_DPK_CTL_EN BIT(28)
9017 #define R_DPK_CFG 0x80B8
9018 #define B_DPK_CFG_IDX GENMASK(14, 12)
9019 #define R_DPK_CFG2 0x80BC
9020 #define B_DPK_CFG2_ST BIT(14)
9021 #define R_DPK_CFG3 0x80C0
9022 #define R_KPATH_CFG 0x80D0
9023 #define B_KPATH_CFG_ED GENMASK(21, 20)
9024 #define R_KIP_RPT1 0x80D4
9025 #define B_KIP_RPT1_SEL GENMASK(21, 16)
9026 #define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)
9027 #define R_SRAM_IQRX 0x80D8
9028 #define R_IDL_MPA 0x80DC
9029 #define B_IDL_DN BIT(31)
9030 #define B_IDL_MD530 BIT(1)
9031 #define B_IDL_MD500 BIT(0)
9032 #define R_GAPK 0x80E0
9033 #define B_GAPK_ADR BIT(0)
9034 #define R_SRAM_IQRX2 0x80E8
9035 #define R_DPK_MPA 0x80EC
9036 #define B_DPK_MPA_T0 BIT(10)
9037 #define B_DPK_MPA_T1 BIT(9)
9038 #define B_DPK_MPA_T2 BIT(8)
9039 #define R_DPK_WR 0x80F4
9040 #define B_DPK_WR_ST BIT(29)
9041 #define R_DPK_TRK 0x80f0
9042 #define B_DPK_TRK_DIS BIT(31)
9043 #define R_RPT_COM 0x80FC
9044 #define B_PRT_COM_SYNERR BIT(30)
9045 #define B_PRT_COM_DCI GENMASK(27, 16)
9046 #define B_PRT_COM_CORV GENMASK(15, 8)
9047 #define B_RPT_COM_RDY GENMASK(15, 0)
9048 #define B_PRT_COM_DCQ GENMASK(11, 0)
9049 #define B_PRT_COM_RXOV BIT(8)
9050 #define B_PRT_COM_GL GENMASK(7, 4)
9051 #define B_PRT_COM_CORI GENMASK(7, 0)
9052 #define B_PRT_COM_RXBB GENMASK(5, 0)
9053 #define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
9054 #define B_PRT_COM_DONE BIT(0)
9055 #define R_COEF_SEL 0x8104
9056 #define R_COEF_SEL_C1 0x8204
9057 #define B_COEF_SEL_IQC BIT(0)
9058 #define B_COEF_SEL_IQC_V1 GENMASK(1, 0)
9059 #define B_COEF_SEL_MDPD BIT(8)
9060 #define B_COEF_SEL_MDPD_V1 GENMASK(9, 8)
9061 #define B_COEF_SEL_EN BIT(31)
9062 #define R_CFIR_SYS 0x8120
9063 #define R_IQK_RES 0x8124
9064 #define B_IQK_RES_K BIT(28)
9065 #define B_IQK_RES_TXCFIR GENMASK(11, 8)
9066 #define B_IQK_RES_RXCFIR GENMASK(3, 0)
9067 #define R_TXIQC 0x8138
9068 #define R_RXIQC 0x813c
9069 #define B_RXIQC_BYPASS BIT(0)
9070 #define B_RXIQC_BYPASS2 BIT(2)
9071 #define B_RXIQC_NEWP GENMASK(19, 8)
9072 #define B_RXIQC_NEWX GENMASK(31, 20)
9073 #define R_KIP 0x8140
9074 #define B_KIP_DBCC BIT(0)
9075 #define B_KIP_RFGAIN BIT(8)
9076 #define R_RFGAIN 0x8144
9077 #define B_RFGAIN_PAD GENMASK(4, 0)
9078 #define B_RFGAIN_TXBB GENMASK(12, 8)
9079 #define R_RFGAIN_BND 0x8148
9080 #define B_RFGAIN_BND GENMASK(4, 0)
9081 #define R_CFIR_MAP 0x8150
9082 #define R_CFIR_LUT 0x8154
9083 #define R_CFIR_LUT_C1 0x8254
9084 #define B_CFIR_LUT_SEL BIT(8)
9085 #define B_CFIR_LUT_SET BIT(4)
9086 #define B_CFIR_LUT_G5 BIT(5)
9087 #define B_CFIR_LUT_G3 BIT(3)
9088 #define B_CFIR_LUT_G2 BIT(2)
9089 #define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
9090 #define B_CFIR_LUT_GP GENMASK(1, 0)
9091 #define R_DPK_GN 0x819C
9092 #define B_DPK_GN_EN GENMASK(17, 16)
9093 #define B_DPK_GN_AG GENMASK(9, 0)
9094 #define R_DPD_V1 0x81a0
9095 #define B_DPD_LBK BIT(7)
9096 #define R_DPD_CH0 0x81AC
9097 #define R_DPD_BND 0x81B4
9098 #define B_DPD_BND_1 GENMASK(24, 16)
9099 #define B_DPD_BND_0 GENMASK(8, 0)
9100 #define R_DPD_CH0A 0x81BC
9101 #define B_DPD_MEN GENMASK(31, 28)
9102 #define B_DPD_ORDER GENMASK(26, 24)
9103 #define B_DPD_ORDER_V1 GENMASK(26, 25)
9104 #define B_DPD_CFG GENMASK(22, 0)
9105 #define B_DPD_SEL GENMASK(13, 8)
9106 #define R_TXAGC_RFK 0x81C4
9107 #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
9108 #define R_DPD_COM 0x81C8
9109 #define B_DPD_COM_OF BIT(15)
9110 #define R_KIP_IQP 0x81CC
9111 #define B_KIP_IQP_SW GENMASK(13, 12)
9112 #define B_KIP_IQP_IQSW GENMASK(5, 0)
9113 #define R_KIP_RPT 0x81D4
9114 #define B_KIP_RPT_SEL GENMASK(21, 16)
9115 #define R_W_COEF 0x81D8
9116 #define R_LOAD_COEF 0x81DC
9117 #define B_LOAD_COEF_MDPD BIT(16)
9118 #define B_LOAD_COEF_CFIR GENMASK(1, 0)
9119 #define B_LOAD_COEF_DI BIT(1)
9120 #define B_LOAD_COEF_AUTO BIT(0)
9121 #define R_DPK_GL 0x81F0
9122 #define B_DPK_GL_A0 GENMASK(31, 28)
9123 #define B_DPK_GL_A1 GENMASK(17, 0)
9124 #define R_RPT_PER 0x81FC
9125 #define B_RPT_PER_KSET GENMASK(31, 29)
9126 #define B_RPT_PER_TSSI GENMASK(28, 16)
9127 #define B_RPT_PER_OF GENMASK(15, 8)
9128 #define B_RPT_PER_TH GENMASK(5, 0)
9129 #define R_IQRSN 0x8220
9130 #define B_IQRSN_K1 BIT(28)
9131 #define B_IQRSN_K2 BIT(16)
9132 #define R_DPD_CH0B 0x82BC
9133 #define R_RXCFIR_P0C0 0x8D40
9134 #define R_RXCFIR_P0C1 0x8D84
9135 #define R_RXCFIR_P0C2 0x8DC8
9136 #define R_RXCFIR_P0C3 0x8E0C
9137 #define R_TXCFIR_P0C0 0x8F50
9138 #define R_TXCFIR_P0C1 0x8F84
9139 #define R_TXCFIR_P0C2 0x8FB8
9140 #define R_TXCFIR_P0C3 0x8FEC
9141 #define R_RXCFIR_P1C0 0x9140
9142 #define R_RXCFIR_P1C1 0x9184
9143 #define R_RXCFIR_P1C2 0x91C8
9144 #define R_RXCFIR_P1C3 0x920C
9145 #define R_TXCFIR_P1C0 0x9350
9146 #define R_TXCFIR_P1C1 0x9384
9147 #define R_TXCFIR_P1C2 0x93B8
9148 #define R_TXCFIR_P1C3 0x93EC
9149 #define R_IQKINF 0x9FE0
9150 #define B_IQKINF_VER GENMASK(31, 24)
9151 #define B_IQKINF_FAIL_RXGRP GENMASK(23, 16)
9152 #define B_IQKINF_FAIL_TXGRP GENMASK(15, 8)
9153 #define B_IQKINF_FAIL GENMASK(3, 0)
9154 #define B_IQKINF_F_RX BIT(3)
9155 #define B_IQKINF_FTX BIT(2)
9156 #define B_IQKINF_FFIN BIT(1)
9157 #define B_IQKINF_FCOR BIT(0)
9158 #define R_IQKCH 0x9FE4
9159 #define B_IQKCH_CH GENMASK(15, 8)
9160 #define B_IQKCH_BW GENMASK(7, 4)
9161 #define B_IQKCH_BAND GENMASK(3, 0)
9162 #define R_IQKINF2 0x9FE8
9163 #define B_IQKINF2_FCNT GENMASK(23, 16)
9164 #define B_IQKINF2_KCNT GENMASK(15, 8)
9165 #define B_IQKINF2_NCTLV GENMASK(7, 0)
9166 #define R_RFK_ST 0xBFF8
9167 #define R_DCOF0 0xC000
9168 #define B_DCOF0_RST BIT(17)
9169 #define B_DCOF0_V GENMASK(4, 1)
9170 #define R_DCOF1 0xC004
9171 #define B_DCOF1_VAL GENMASK(31, 20)
9172 #define B_DCOF1_RST BIT(17)
9173 #define B_DCOF1_S BIT(0)
9174 #define R_DCOF8 0xC020
9175 #define B_DCOF8_V GENMASK(4, 1)
9176 #define R_DCOF9 0xC024
9177 #define B_DCOF9_VAL GENMASK(31, 20)
9178 #define B_DCOF9_RST BIT(17)
9179 #define R_DACK_S0P0 0xC040
9180 #define B_DACK_S0P0_OK BIT(31)
9181 #define R_DACK_BIAS00 0xc048
9182 #define B_DACK_BIAS00 GENMASK(11, 2)
9183 #define R_DACK_S0P2 0xC05C
9184 #define B_DACK_S0M0 GENMASK(31, 24)
9185 #define B_DACK_S0P2_OK BIT(2)
9186 #define R_DACK_DADCK00 0xC060
9187 #define B_DACK_DADCK00 GENMASK(31, 24)
9188 #define R_DACK_S0P1 0xC064
9189 #define B_DACK_S0P1_OK BIT(31)
9190 #define R_DACK_BIAS01 0xC06C
9191 #define B_DACK_BIAS01 GENMASK(11, 2)
9192 #define R_DACK_S0P3 0xC080
9193 #define B_DACK_S0M1 GENMASK(31, 24)
9194 #define B_DACK_S0P3_OK BIT(2)
9195 #define R_DACK_DADCK01 0xC084
9196 #define B_DACK_DADCK01 GENMASK(31, 24)
9197 #define R_DRCK_FH 0xC094
9198 #define B_DRCK_LAT BIT(9)
9199 #define R_DRCK 0xC0C4
9200 #define B_DRCK_MUL GENMASK(21, 17)
9201 #define B_DRCK_IDLE BIT(9)
9202 #define B_DRCK_EN BIT(6)
9203 #define B_DRCK_VAL GENMASK(4, 0)
9204 #define R_DRCK_RES 0xC0C8
9205 #define B_DRCK_RES GENMASK(19, 15)
9206 #define B_DRCK_POL BIT(3)
9207 #define R_DRCK_V1 0xC0CC
9208 #define B_DRCK_V1_SEL BIT(9)
9209 #define B_DRCK_V1_KICK BIT(6)
9210 #define B_DRCK_V1_CV GENMASK(4, 0)
9211 #define R_DRCK_RS 0xC0D0
9212 #define B_DRCK_RS_LPS GENMASK(19, 15)
9213 #define B_DRCK_RS_DONE BIT(3)
9214 #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
9215 #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
9216 #define R_P0_CFCH_BW0 0xC0D4
9217 #define B_P0_CFCH_BW0 GENMASK(27, 26)
9218 #define B_P0_CFCH_EN GENMASK(14, 11)
9219 #define B_P0_CFCH_CTL GENMASK(10, 7)
9220 #define R_P0_CFCH_BW1 0xC0D8
9221 #define B_P0_CFCH_EX BIT(13)
9222 #define B_P0_CFCH_BW1 GENMASK(8, 5)
9223 #define R_WDADC 0xC0E4
9224 #define B_WDADC_SEL GENMASK(5, 4)
9225 #define R_ADCMOD 0xC0E8
9226 #define B_ADCMOD_LP GENMASK(31, 16)
9227 #define R_DCIM 0xC0EC
9228 #define B_DCIM_RC GENMASK(23, 16)
9229 #define B_DCIM_FR GENMASK(14, 13)
9230 #define R_ADDCK0D 0xC0F0
9231 #define B_ADDCK0D_VAL2 GENMASK(31, 26)
9232 #define B_ADDCK0D_VAL GENMASK(25, 16)
9233 #define B_ADDCK_DS BIT(16)
9234 #define R_ADDCK0 0xC0F4
9235 #define B_ADDCK0_TRG BIT(11)
9236 #define B_ADDCK0_IQ BIT(10)
9237 #define B_ADDCK0 GENMASK(9, 8)
9238 #define B_ADDCK0_MAN GENMASK(5, 4)
9239 #define B_ADDCK0_EN BIT(4)
9240 #define B_ADDCK0_VAL GENMASK(3, 0)
9241 #define B_ADDCK0_RST BIT(2)
9242 #define R_ADDCK0_RL 0xC0F8
9243 #define B_ADDCK0_RLS GENMASK(29, 28)
9244 #define B_ADDCK0_RL1 GENMASK(27, 18)
9245 #define B_ADDCK0_RL0 GENMASK(17, 8)
9246 #define R_ADDCKR0 0xC0FC
9247 #define B_ADDCKR0_A0 GENMASK(19, 10)
9248 #define B_ADDCKR0_DC GENMASK(15, 4)
9249 #define B_ADDCKR0_A1 GENMASK(9, 0)
9250 #define R_DACK10 0xC100
9251 #define B_DACK10_RST BIT(17)
9252 #define B_DACK10 GENMASK(4, 1)
9253 #define R_DACK1_K 0xc104
9254 #define B_DACK1_VAL GENMASK(31, 20)
9255 #define B_DACK1_RST BIT(17)
9256 #define B_DACK1_EN BIT(0)
9257 #define R_DACK11 0xC120
9258 #define B_DACK11 GENMASK(4, 1)
9259 #define R_DACK2_K 0xC124
9260 #define B_DACK2_VAL GENMASK(31, 20)
9261 #define B_DACK2_RST BIT(17)
9262 #define B_DACK2_EN BIT(0)
9263 #define R_DACK_S1P0 0xC140
9264 #define B_DACK_S1P0_OK BIT(31)
9265 #define R_DACK_BIAS10 0xC148
9266 #define B_DACK_BIAS10 GENMASK(11, 2)
9267 #define R_DACK10S 0xC15C
9268 #define B_DACK10S GENMASK(31, 24)
9269 #define R_DACK_S1P2 0xC15C
9270 #define B_DACK_S1P2_OK BIT(2)
9271 #define R_DACK_DADCK10 0xC160
9272 #define B_DACK_DADCK10 GENMASK(31, 24)
9273 #define R_DACK_S1P1 0xC164
9274 #define B_DACK_S1P1_OK BIT(31)
9275 #define R_DACK_BIAS11 0xC16C
9276 #define B_DACK_BIAS11 GENMASK(11, 2)
9277 #define R_DACK11S 0xC180
9278 #define B_DACK11S GENMASK(31, 24)
9279 #define R_DACK_S1P3 0xC180
9280 #define B_DACK_S1P3_OK BIT(2)
9281 #define R_DACK_DADCK11 0xC184
9282 #define B_DACK_DADCK11 GENMASK(31, 24)
9283 #define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
9284 #define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
9285 #define R_PATH0_BW_SEL_V1 0xC0D8
9286 #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
9287 #define R_PATH1_BW_SEL_V1 0xC1D8
9288 #define B_PATH1_BW_SEL_EX BIT(13)
9289 #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
9290 #define R_ADDCK1D 0xC1F0
9291 #define B_ADDCK1D_VAL2 GENMASK(31, 26)
9292 #define B_ADDCK1D_VAL GENMASK(25, 16)
9293 #define R_ADDCK1 0xC1F4
9294 #define B_ADDCK1_TRG BIT(11)
9295 #define B_ADDCK1 GENMASK(9, 8)
9296 #define B_ADDCK1_MAN GENMASK(5, 4)
9297 #define B_ADDCK1_EN BIT(4)
9298 #define B_ADDCK1_RST BIT(2)
9299 #define R_ADDCK1_RL 0xC1F8
9300 #define B_ADDCK1_RLS GENMASK(29, 28)
9301 #define B_ADDCK1_RL1 GENMASK(27, 18)
9302 #define B_ADDCK1_RL0 GENMASK(17, 8)
9303 #define R_ADDCKR1 0xC1fC
9304 #define B_ADDCKR1_A0 GENMASK(19, 10)
9305 #define B_ADDCKR1_A1 GENMASK(9, 0)
9306 #define R_DACKN0_CTL 0xC210
9307 #define B_DACKN0_EN BIT(0)
9308 #define B_DACKN0_V GENMASK(21, 14)
9309 #define R_DACKN1_CTL 0xC224
9310 #define B_DACKN1_V GENMASK(21, 14)
9311 #define B_DACKN1_ON BIT(0)
9312 #define R_DACKN2_CTL 0xC238
9313 #define B_DACKN2_ON BIT(0)
9314 #define R_DACKN3_CTL 0xC24C
9315 #define B_DACKN3_ON BIT(0)
9316 #define R_GAIN_MAP0 0xE44C
9317 #define B_GAIN_MAP0_EN BIT(0)
9318 #define R_GAIN_MAP1 0xE54C
9319 #define B_GAIN_MAP1_EN BIT(0)
9320 #define R_GOTX_IQKDPK_C0 0xE464
9321 #define R_GOTX_IQKDPK_C1 0xE564
9322 #define B_GOTX_IQKDPK GENMASK(28, 27)
9323 #define R_IQK_DPK_PRST 0xE4AC
9324 #define R_IQK_DPK_PRST_C1 0xE5AC
9325 #define B_IQK_DPK_PRST BIT(27)
9326 #define R_TXPWR_RSTA 0xE60C
9327 #define B_TXPWR_RSTA BIT(16)
9328 #define R_TSSI_PWR_P0 0xE610
9329 #define R_TSSI_PWR_P1 0xE710
9330 #define B_TSSI_CONT_EN BIT(3)
9331 #define R_TSSI_MAP_OFST_P0 0xE620
9332 #define R_TSSI_MAP_OFST_P1 0xE720
9333 #define B_TSSI_MAP_OFST_OFDM GENMASK(17, 9)
9334 #define B_TSSI_MAP_OFST_CCK GENMASK(26, 18)
9335 #define R_TXAGC_REF0_P0 0xE628
9336 #define R_TXAGC_REF0_P1 0xE728
9337 #define B_TXAGC_REF0_OFDM_DBM GENMASK(8, 0)
9338 #define B_TXAGC_REF0_CCK_DBM GENMASK(17, 9)
9339 #define B_TXAGC_REF0_OFDM_CW GENMASK(26, 18)
9340 #define R_TXAGC_REF1_P0 0xE62C
9341 #define R_TXAGC_REF1_P1 0xE72C
9342 #define B_TXAGC_REF1_CCK_CW GENMASK(8, 0)
9343 #define R_TXPWR_RSTB 0xE70C
9344 #define B_TXPWR_RSTB BIT(16)
9345 
9346 /* WiFi CPU local domain */
9347 #define R_AX_WDT_CTRL 0x0040
9348 #define B_AX_WDT_EN BIT(31)
9349 #define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29)
9350 #define B_AX_IO_HANG_IMR BIT(27)
9351 #define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26)
9352 #define B_AX_IO_HANG_DMAC_EN BIT(25)
9353 #define B_AX_WDT_CLR BIT(16)
9354 #define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
9355 #define WDT_CTRL_ALL_DIS 0
9356 
9357 #define R_AX_WDT_STATUS 0x0044
9358 #define B_AX_FS_WDT_INT BIT(8)
9359 #define B_AX_FS_WDT_INT_MSK BIT(0)
9360 
9361 #endif
9362