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Searched refs:SYS_FIELD_GET (Results 1 – 8 of 8) sorted by relevance

/linux/arch/arm64/include/asm/
H A Dcache.h58 #define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
74 return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype()); in cache_type_cwg()
H A Dkvm_mmu.h239 iminline = SYS_FIELD_GET(CTR_EL0, IminLine, ctr) + 2; in __invalidate_icache_max_range()
H A Dkvm_emulate.h683 SYS_FIELD_GET(CPACR_ELx, xen, \
H A Dsysreg.h1223 #define SYS_FIELD_GET(reg, field, val) \ macro
/linux/arch/arm64/kvm/hyp/vhe/
H A Dswitch.c125 if (!(SYS_FIELD_GET(CPACR_ELx, FPEN, cptr) & BIT(0))) in __activate_cptr_traps()
127 if (!(SYS_FIELD_GET(CPACR_ELx, ZEN, cptr) & BIT(0))) in __activate_cptr_traps()
/linux/arch/arm64/kvm/
H A Dsys_regs.c237 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); in get_min_cache_line_size()
239 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); in get_min_cache_line_size()
1050 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, in access_pmu_evcntr()
1101 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); in access_pmu_evtyper()
1756 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); in set_id_aa64dfr0_el1()
1757 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); in set_id_aa64dfr0_el1()
1805 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); in set_id_dfr0_el1()
1806 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); in set_id_dfr0_el1()
2258 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; in access_zcr_el2()
3302 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | in trap_dbgdidr()
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H A Dpmu-emul.c57 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, dfr0); in kvm_pmu_event_mask()
/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h830 #define SYS_FIELD_GET(reg, field, val) \ macro