Searched refs:STMP_OFFSET_REG_CLR (Results 1 – 7 of 7) sorted by relevance
101 ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_map_ts_channel()125 ts->base + LRADC_CH(ch) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_channel()141 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_channel()183 ts->base + LRADC_CH(ch1) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()185 ts->base + LRADC_CH(ch2) + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()195 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_ts_pressure()283 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_setup_touch_detection()305 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_x_pos()331 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_y_pos()357 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_prepare_pressure()[all …]
89 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()91 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR); in stmp3xxx_wdt_set_timeout()176 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_interrupt()199 STMP_OFFSET_REG_CLR); in stmp3xxx_alarm_irq_enable()201 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_alarm_irq_enable()242 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_remove()347 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_probe()351 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_probe()390 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); in stmp3xxx_rtc_resume()
30 writel(mask, addr + STMP_OFFSET_REG_CLR); in stmp_clear_poll_bit()49 writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR); in stmp_reset_block()
70 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()100 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
12 #define STMP_OFFSET_REG_CLR 0x8 macro
71 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); in timrot_irq_disable()83 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); in timrot_irq_acknowledge()
289 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_dma_resume_chan()292 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); in mxs_dma_resume_chan()338 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_dma_int_handler()353 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_dma_int_handler()