1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 4 Header file for stmmac platform data 5 6 Copyright (C) 2009 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 *******************************************************************************/ 11 12 #ifndef __STMMAC_PLATFORM_DATA 13 #define __STMMAC_PLATFORM_DATA 14 15 #include <linux/platform_device.h> 16 #include <linux/phylink.h> 17 18 #define MTL_MAX_RX_QUEUES 8 19 #define MTL_MAX_TX_QUEUES 8 20 #define STMMAC_CH_MAX 8 21 22 #define STMMAC_RX_COE_NONE 0 23 #define STMMAC_RX_COE_TYPE1 1 24 #define STMMAC_RX_COE_TYPE2 2 25 26 /* Define the macros for CSR clock range parameters to be passed by 27 * platform code. 28 * This could also be configured at run time using CPU freq framework. */ 29 30 /* MDC Clock Selection define*/ 31 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 32 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 33 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 34 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 35 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 36 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 37 38 /* MTL algorithms identifiers */ 39 #define MTL_TX_ALGORITHM_WRR 0x0 40 #define MTL_TX_ALGORITHM_WFQ 0x1 41 #define MTL_TX_ALGORITHM_DWRR 0x2 42 #define MTL_TX_ALGORITHM_SP 0x3 43 #define MTL_RX_ALGORITHM_SP 0x4 44 #define MTL_RX_ALGORITHM_WSP 0x5 45 46 /* RX/TX Queue Mode */ 47 #define MTL_QUEUE_AVB 0x0 48 #define MTL_QUEUE_DCB 0x1 49 50 /* The MDC clock could be set higher than the IEEE 802.3 51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider 52 * of value different than the above defined values. The resultant MDIO 53 * clock frequency of 12.5 MHz is applicable for the interfacing chips 54 * supporting higher MDC clocks. 55 * The MDC clock selection macros need to be defined for MDC clock rate 56 * of 12.5 MHz, corresponding to the following selection. 57 */ 58 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 59 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 60 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 61 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 62 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 63 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 64 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 65 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 66 67 /* AXI DMA Burst length supported */ 68 #define DMA_AXI_BLEN_4 (1 << 1) 69 #define DMA_AXI_BLEN_8 (1 << 2) 70 #define DMA_AXI_BLEN_16 (1 << 3) 71 #define DMA_AXI_BLEN_32 (1 << 4) 72 #define DMA_AXI_BLEN_64 (1 << 5) 73 #define DMA_AXI_BLEN_128 (1 << 6) 74 #define DMA_AXI_BLEN_256 (1 << 7) 75 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 78 79 struct stmmac_priv; 80 81 /* Platfrom data for platform device structure's platform_data field */ 82 83 struct stmmac_mdio_bus_data { 84 unsigned int phy_mask; 85 unsigned int pcs_mask; 86 unsigned int default_an_inband; 87 int *irqs; 88 int probed_phy_irq; 89 bool needs_reset; 90 }; 91 92 struct stmmac_dma_cfg { 93 int pbl; 94 int txpbl; 95 int rxpbl; 96 bool pblx8; 97 int fixed_burst; 98 int mixed_burst; 99 bool aal; 100 bool eame; 101 bool multi_msi_en; 102 bool dche; 103 bool atds; 104 }; 105 106 #define AXI_BLEN 7 107 struct stmmac_axi { 108 bool axi_lpi_en; 109 bool axi_xit_frm; 110 u32 axi_wr_osr_lmt; 111 u32 axi_rd_osr_lmt; 112 bool axi_kbbe; 113 u32 axi_blen[AXI_BLEN]; 114 bool axi_fb; 115 bool axi_mb; 116 bool axi_rb; 117 }; 118 119 struct stmmac_rxq_cfg { 120 u8 mode_to_use; 121 u32 chan; 122 u8 pkt_route; 123 bool use_prio; 124 u32 prio; 125 }; 126 127 struct stmmac_txq_cfg { 128 u32 weight; 129 bool coe_unsupported; 130 u8 mode_to_use; 131 /* Credit Base Shaper parameters */ 132 u32 send_slope; 133 u32 idle_slope; 134 u32 high_credit; 135 u32 low_credit; 136 bool use_prio; 137 u32 prio; 138 int tbs_en; 139 }; 140 141 struct stmmac_safety_feature_cfg { 142 u32 tsoee; 143 u32 mrxpee; 144 u32 mestee; 145 u32 mrxee; 146 u32 mtxee; 147 u32 epsi; 148 u32 edpp; 149 u32 prtyen; 150 u32 tmouten; 151 }; 152 153 /* Addresses that may be customized by a platform */ 154 struct dwmac4_addrs { 155 u32 dma_chan; 156 u32 dma_chan_offset; 157 u32 mtl_chan; 158 u32 mtl_chan_offset; 159 u32 mtl_ets_ctrl; 160 u32 mtl_ets_ctrl_offset; 161 u32 mtl_txq_weight; 162 u32 mtl_txq_weight_offset; 163 u32 mtl_send_slp_cred; 164 u32 mtl_send_slp_cred_offset; 165 u32 mtl_high_cred; 166 u32 mtl_high_cred_offset; 167 u32 mtl_low_cred; 168 u32 mtl_low_cred_offset; 169 }; 170 171 #define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0) 172 #define STMMAC_FLAG_SPH_DISABLE BIT(1) 173 #define STMMAC_FLAG_USE_PHY_WOL BIT(2) 174 #define STMMAC_FLAG_HAS_SUN8I BIT(3) 175 #define STMMAC_FLAG_TSO_EN BIT(4) 176 #define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5) 177 #define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6) 178 #define STMMAC_FLAG_MULTI_MSI_EN BIT(7) 179 #define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8) 180 #define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9) 181 #define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10) 182 #define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11) 183 #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12) 184 185 struct plat_stmmacenet_data { 186 int bus_id; 187 int phy_addr; 188 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media 189 * ^ ^ 190 * mac_interface phy_interface 191 * 192 * mac_interface is the MAC-side interface, which may be the same 193 * as phy_interface if there is no intervening PCS. If there is a 194 * PCS, then mac_interface describes the interface mode between the 195 * MAC and PCS, and phy_interface describes the interface mode 196 * between the PCS and PHY. 197 */ 198 phy_interface_t mac_interface; 199 /* phy_interface is the PHY-side interface - the interface used by 200 * an attached PHY. 201 */ 202 phy_interface_t phy_interface; 203 struct stmmac_mdio_bus_data *mdio_bus_data; 204 struct device_node *phy_node; 205 struct fwnode_handle *port_node; 206 struct device_node *mdio_node; 207 struct stmmac_dma_cfg *dma_cfg; 208 struct stmmac_safety_feature_cfg *safety_feat_cfg; 209 int clk_csr; 210 int has_gmac; 211 int enh_desc; 212 int tx_coe; 213 int rx_coe; 214 int bugged_jumbo; 215 int pmt; 216 int force_sf_dma_mode; 217 int force_thresh_dma_mode; 218 int riwt_off; 219 int max_speed; 220 int maxmtu; 221 int multicast_filter_bins; 222 int unicast_filter_entries; 223 int tx_fifo_size; 224 int rx_fifo_size; 225 u32 host_dma_width; 226 u32 rx_queues_to_use; 227 u32 tx_queues_to_use; 228 u8 rx_sched_algorithm; 229 u8 tx_sched_algorithm; 230 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; 231 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; 232 void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode); 233 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr); 234 int (*serdes_powerup)(struct net_device *ndev, void *priv); 235 void (*serdes_powerdown)(struct net_device *ndev, void *priv); 236 void (*speed_mode_2500)(struct net_device *ndev, void *priv); 237 void (*ptp_clk_freq_config)(struct stmmac_priv *priv); 238 int (*init)(struct platform_device *pdev, void *priv); 239 void (*exit)(struct platform_device *pdev, void *priv); 240 struct mac_device_info *(*setup)(void *priv); 241 int (*clks_config)(void *priv, bool enabled); 242 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system, 243 void *ctx); 244 void (*dump_debug_regs)(void *priv); 245 int (*pcs_init)(struct stmmac_priv *priv); 246 void (*pcs_exit)(struct stmmac_priv *priv); 247 struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv, 248 phy_interface_t interface); 249 void *bsp_priv; 250 struct clk *stmmac_clk; 251 struct clk *pclk; 252 struct clk *clk_ptp_ref; 253 unsigned int clk_ptp_rate; 254 unsigned int clk_ref_rate; 255 unsigned int mult_fact_100ns; 256 s32 ptp_max_adj; 257 u32 cdc_error_adj; 258 struct reset_control *stmmac_rst; 259 struct reset_control *stmmac_ahb_rst; 260 struct stmmac_axi *axi; 261 int has_gmac4; 262 int rss_en; 263 int mac_port_sel_speed; 264 int has_xgmac; 265 u8 vlan_fail_q; 266 unsigned int eee_usecs_rate; 267 struct pci_dev *pdev; 268 int int_snapshot_num; 269 int msi_mac_vec; 270 int msi_wol_vec; 271 int msi_lpi_vec; 272 int msi_sfty_ce_vec; 273 int msi_sfty_ue_vec; 274 int msi_rx_base_vec; 275 int msi_tx_base_vec; 276 const struct dwmac4_addrs *dwmac4_addrs; 277 unsigned int flags; 278 }; 279 #endif 280