Searched refs:STATUS_REG (Results 1 – 7 of 7) sorted by relevance
14 #define STATUS_REG 0x00000004 macro42 if (readl(trng->mem + STATUS_REG) == TRNG_NEW_RAND_AVAILABLE) { in xiphera_trng_read()81 if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) { in xiphera_trng_probe()87 if (readl(trng->mem + STATUS_REG) != TRNG_ACK_RESET) { in xiphera_trng_probe()102 if (readl(trng->mem + STATUS_REG) != TRNG_SUCCESSFUL_STARTUP) { in xiphera_trng_probe()104 if (readl(trng->mem + STATUS_REG) == TRNG_FAILED_STARTUP) { in xiphera_trng_probe()
28 #define STATUS_REG 0x14 macro91 val = readl(config->ioaddr + STATUS_REG); in spear_rtc_clear_interrupt()93 writel(val, config->ioaddr + STATUS_REG); in spear_rtc_clear_interrupt()126 if ((readl(config->ioaddr + STATUS_REG)) & STATUS_FAIL) in is_write_complete()141 status = readl(config->ioaddr + STATUS_REG); in rtc_wait_not_busy()157 irq_data = readl(config->ioaddr + STATUS_REG); in spear_rtc_irq()
34 #define STATUS_REG 0x2C /* STATUS Register */ macro164 status = i2c_smbus_read_byte_data(client, STATUS_REG); in ml86v7667_querystd()181 status_reg = i2c_smbus_read_byte_data(client, STATUS_REG); in ml86v7667_g_input_status()349 val = i2c_smbus_read_byte_data(client, STATUS_REG); in ml86v7667_init()
71 #define STATUS_REG 0x12 /* read only */ macro148 status = inw(dev->iobase + STATUS_REG); in a2150_interrupt()570 status = inw(dev->iobase + STATUS_REG); in a2150_ai_eoc()676 int id = ID_BITS(inw(dev->iobase + STATUS_REG)); in a2150_probe()747 if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0) in a2150_attach()
111 #define STATUS_REG 4 /* ro */ macro
129 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); in g_NCR5380_trigger_irq()
698 STATUS_REG = 1, enumerator