| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.h | 35 SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \
36 SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \
37 SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \
38 SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \
39 SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id), \
40 SRI_ARR(DCHUBP_CNTL, HUBP, id), \
41 SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \
42 SRI_ARR(HUBPREQ_DEBUG, HUBP, id), \
43 SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \
44 SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \
[all …]
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| H A D | dcn401_resource.c | 115 #define SRI_ARR(reg_name, block, id)\ macro
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.h | 52 SRI_ARR(FMT_422_CONTROL, FMT, id), \
53 SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)
60 SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \
61 SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
62 SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \
63 SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
64 SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
65 SRI_ARR(VPG_MEM_PWR, VPG, id)
68 SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
69 SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
[all …]
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| H A D | dcn35_resource.c | 145 #define SRI_ARR(reg_name, block, id)\ macro
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 211 SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
212 SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
213 SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
214 SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \
215 SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
216 SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
217 SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
218 SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \
219 SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
220 SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
[all …]
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| H A D | dcn32_resource.c | 129 #define SRI_ARR(reg_name, block, id)\ macro
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| H A D | dcn401_hubp.h | 39 SRI_ARR(HUBP_3DLUT_ADDRESS_HIGH, CURSOR0_, inst),\
40 SRI_ARR(HUBP_3DLUT_ADDRESS_LOW, CURSOR0_, inst),\
41 SRI_ARR(HUBP_3DLUT_CONTROL, CURSOR0_, inst),\
42 SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, inst)
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 130 #define SRI_ARR(reg_name, block, id)\ macro
|