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Searched refs:SQ_WAVE_STATUS__VALID_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h12507 #define SQ_WAVE_STATUS__VALID_MASK 0x10000 macro
H A Dgfx_8_1_sh_mask.h14785 #define SQ_WAVE_STATUS__VALID_MASK 0x10000 macro
H A Dgfx_8_0_sh_mask.h14387 #define SQ_WAVE_STATUS__VALID_MASK 0x10000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28451 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_9_1_sh_mask.h29663 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_9_2_1_sh_mask.h29989 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_9_4_2_sh_mask.h32720 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_11_5_0_sh_mask.h36398 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_11_0_0_sh_mask.h41469 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_12_0_0_sh_mask.h40202 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_10_1_0_sh_mask.h42764 #define SQ_WAVE_STATUS__VALID_MASK … macro
H A Dgc_11_0_3_sh_mask.h44506 #define SQ_WAVE_STATUS__VALID_MASK … macro