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Searched refs:SQ_WAVE_STATUS__ECC_ERR_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h9968 #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L macro
H A Dgfx_7_2_sh_mask.h12509 #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 macro
H A Dgfx_8_1_sh_mask.h14787 #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 macro
H A Dgfx_8_0_sh_mask.h14389 #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28452 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro
H A Dgc_9_1_sh_mask.h29664 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro
H A Dgc_9_2_1_sh_mask.h29990 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro
H A Dgc_9_4_2_sh_mask.h32721 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro
H A Dgc_11_5_0_sh_mask.h36399 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro
H A Dgc_11_0_0_sh_mask.h41470 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro
H A Dgc_10_1_0_sh_mask.h42765 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro
H A Dgc_11_0_3_sh_mask.h44507 #define SQ_WAVE_STATUS__ECC_ERR_MASK … macro