Searched refs:SPRN_L2CR (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/powerpc/platforms/powermac/ |
| H A D | cache.S | 99 mfspr r5,SPRN_L2CR
105 1: mtspr SPRN_L2CR,r3
139 1: mtspr SPRN_L2CR,r5
151 mtspr SPRN_L2CR,r4
156 1: mfspr r3,SPRN_L2CR
163 mtspr SPRN_L2CR,r4
271 mfspr r3,SPRN_L2CR
278 1: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
290 mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
291 3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
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| /linux/arch/powerpc/kernel/ |
| H A D | l2cr_6xx.S | 123 mfspr r4,SPRN_L2CR
197 mtspr SPRN_L2CR,r3
210 mtspr SPRN_L2CR,r3
217 10: mfspr r3,SPRN_L2CR
224 3: mfspr r3,SPRN_L2CR
230 mtspr SPRN_L2CR,r3
239 mtspr SPRN_L2CR,r3
269 mfspr r3,SPRN_L2CR
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| H A D | cpu_setup_6xx.S | 291 mfspr r3,SPRN_L2CR
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| /linux/arch/powerpc/kvm/ |
| H A D | book3s_emulate.c | 821 case SPRN_L2CR: in kvmppc_core_emulate_mtspr_pr()
988 case SPRN_L2CR: in kvmppc_core_emulate_mfspr_pr()
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| /linux/arch/powerpc/include/asm/ |
| H A D | reg.h | 673 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */ macro
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