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Searched refs:SPRN_L1CSR1 (Results 1 – 5 of 5) sorted by relevance

/linux/arch/powerpc/kernel/
H A Dcpu_setup_e500.S22 mfspr r0, SPRN_L1CSR1
27 mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
H A Dtraps.c630 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); in machine_check_e500mc()
631 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) in machine_check_e500mc()
/linux/arch/powerpc/mm/nohash/
H A De500.c247 tmp = mfspr(SPRN_L1CSR1); in flush_instruction_cache()
249 mtspr(SPRN_L1CSR1, tmp); in flush_instruction_cache()
/linux/arch/powerpc/kvm/
H A De500_emulate.c252 case SPRN_L1CSR1: in kvmppc_core_emulate_mtspr_e500()
381 case SPRN_L1CSR1: in kvmppc_core_emulate_mfspr_e500()
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h166 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ macro