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Searched refs:SPI_GDBG_WAVE_CNTL__STALL_RA_MASK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8855 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h10871 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h10473 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12325 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_9_2_1_sh_mask.h13501 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_9_4_3_sh_mask.h15849 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_9_4_2_sh_mask.h24934 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_11_5_0_sh_mask.h20908 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_11_0_0_sh_mask.h24870 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_12_0_0_sh_mask.h32661 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_10_1_0_sh_mask.h19706 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_11_0_3_sh_mask.h27336 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK … macro
H A Dgc_10_3_0_sh_mask.h18055 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L macro