Searched refs:SOR_PWM_CTL_CLK_SEL (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/gpu/drm/tegra/ | ||
| H A D | sor.h | 196 #define SOR_PWM_CTL_CLK_SEL (1 << 30) macro |
| H A D | sor.c | 982 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm() |