Searched refs:SOFT_RST (Results 1 – 4 of 4) sorted by relevance
3 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
71 #define SOFT_RST BIT(0) /* Core Reset */ macro640 !(regval & SOFT_RST), 1, 10000); in i3c_hci_init()643 reg_write(RESET_CONTROL, SOFT_RST); in i3c_hci_init()645 !(regval & SOFT_RST), 1, 10000); in i3c_hci_init()
108 #define SOFT_RST 0x1 macro
474 emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, SOFT_RST); in emac_mac_reset()