Searched refs:SOCFPGA_PLL_DIVQ_MASK (Results 1 – 1 of 1) sorted by relevance
28 #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 macro52 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()