Searched refs:SOCFPGA_PLL_DIVF_MASK (Results 1 – 2 of 2) sorted by relevance
21 #define SOCFPGA_PLL_DIVF_MASK 0x00001FFF macro43 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
26 #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8 macro51 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()