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Searched refs:SOC15_WAIT_ON_RREG (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c584 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v4_0_5_disable_static_power_gating()
588 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
593 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
598 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
604 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
608 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
612 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
616 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
650 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
655 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
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H A Dvcn_v3_0.c694 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, in vcn_v3_0_disable_static_power_gating()
712 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); in vcn_v3_0_disable_static_power_gating()
767 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v3_0_enable_static_power_gating()
818 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
1604 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1609 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1612 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1615 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1617 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1648 r = SOC15_WAIT_ON_RREG(VC in vcn_v3_0_stop()
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H A Dvcn_v4_0.c641 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, in vcn_v4_0_disable_static_power_gating()
663 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); in vcn_v4_0_disable_static_power_gating()
727 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v4_0_enable_static_power_gating()
779 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_disable_clock_gating()
1578 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
1583 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_stop_dpg_mode()
1585 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
1625 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v4_0_stop()
1633 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); in vcn_v4_0_stop()
1643 r = SOC15_WAIT_ON_RREG(VC in vcn_v4_0_stop()
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H A Dumsch_mm_v4_0.c67 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_load_microcode()
164 r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF); in umsch_mm_v4_0_load_microcode()
261 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_ring_stop()
H A Dvcn_v5_0_1.c643 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, in vcn_v5_0_1_pause_dpg_mode()
1146 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v5_0_1_stop_dpg_mode()
1151 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v5_0_1_stop_dpg_mode()
1189 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v5_0_1_stop()
1197 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); in vcn_v5_0_1_stop()
1207 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); in vcn_v5_0_1_stop()
1499 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v5_0_1_process_interrupt()
H A Dvcn_v4_0_3.c677 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_3_disable_clock_gating()
1375 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1380 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_3_stop_dpg_mode()
1382 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1423 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, in vcn_v4_0_3_stop()
1432 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, in vcn_v4_0_3_stop()
1443 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, in vcn_v4_0_3_stop()
1510 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1519 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, in vcn_v4_0_3_unified_ring_get_wptr()
1841 ret = SOC15_WAIT_ON_RREG(VC in vcn_v4_0_3_set_ras_interrupt_state()
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H A Dvpe_v6_1.c292 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ_6_1_1, 0, in vpe_v_6_1_ring_stop()
296 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ, 0, in vpe_v_6_1_ring_stop()
H A Dsoc15_common.h100 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ macro