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Searched refs:SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h1486 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 macro
H A Ddce_11_0_sh_mask.h1424 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 macro
H A Ddce_10_0_sh_mask.h1516 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 macro
H A Ddce_11_2_sh_mask.h1552 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 macro
H A Ddce_12_0_sh_mask.h2606 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1308 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_1_0_sh_mask.h3605 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h2762 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h2106 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h8114 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h8135 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h5597 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h6192 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h10344 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h2177 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h2374 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h2249 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_4_1_0_sh_mask.h3110 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h2763 #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … macro