Searched refs:SG2042_DIV_HWS (Results 1 – 1 of 1) sorted by relevance
341 #define SG2042_DIV_HWS(_id, _name, _parent, \ macro485 SG2042_DIV_HWS(DIV_CLK_MPLL_RP_CPU_NORMAL_0,488 SG2042_DIV_HWS(DIV_CLK_FPLL_RP_CPU_NORMAL_1,492 SG2042_DIV_HWS(DIV_CLK_MPLL_AXI_DDR_0,495 SG2042_DIV_HWS(DIV_CLK_FPLL_AXI_DDR_1,598 SG2042_DIV_HWS(DIV_CLK_FPLL_TOP_RP_CMN_DIV2,