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Searched refs:SF (Results 1 – 25 of 32) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h136 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
137 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
138 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
139 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
140 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
142 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
143 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
144 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
145 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.h84 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
85 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
86 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
87 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
88 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
89 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
90 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
91 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
92 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
93 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/
H A Ddcn20_mmhubbub.h91 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
92 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
93 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
94 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
95 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
96 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
97 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
98 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
99 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
100 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h47 #define SF(reg_name, field_name, post_fix)\ macro
85 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
86 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
87 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
88 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
89 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
91 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
92 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
93 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.h46 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
47 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
48 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
49 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
50 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
51 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
52 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
53 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
54 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
55 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.h138 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
139 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
140 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
141 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
142 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
143 SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
144 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
145 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
146 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
147 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ macro
49 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
50 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
56 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
[all …]
H A Ddce_mem_input.h247 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
248 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
275 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
276 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
322 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
323 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
324 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
325 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
326 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
330 SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.h41 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
42 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
43 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
44 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
45 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh)…
46 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh…
47 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
48 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/
H A Ddcn35_mmhubbub.h39 SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_TEST_CLK_SEL, mask_sh), \
40 SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_R_MMHUBBUB_GATE_DIS, mask_sh), \
41 SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_G_WBIF0_GATE_DIS, mask_sh), \
42 SF(MMHUBBUB_CLOCK_CNTL, SOCCLK_G_WBIF0_GATE_DIS, mask_sh), \
43 SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, mask_sh)
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.h44 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
45 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
46 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
47 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\
48 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh)
/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
H A Dswitchdev.rst49 device, and by default all the SF auxiliary devices are disabled.
50 This will allow user to configure the SF before the SF have been fully probed,
55 - Create SF::
64 - Now, in order to fully probe the SF, use devlink reload::
160 The mlx5 driver provides a mechanism to setup PCI VF/SF function attributes in
164 configuration of the PCI VF/SF is supported through devlink eswitch port.
166 Port function attributes should be set before PCI VF/SF is enumerated by the
180 PCI devices/SF.
213 SF state setup
216 To use the SF, the user must activate the SF using the SF function state
[all …]
H A Dtracepoints.rst152 SF tracepoints:
154 - mlx5_sf_add: trace addition of the SF port::
161 - mlx5_sf_free: trace freeing of the SF port::
168 - mlx5_sf_activate: trace activation of the SF port::
175 - mlx5_sf_deactivate: trace deactivation of the SF port::
182 - mlx5_sf_hwc_alloc: trace allocating of the hardware SF context::
189 - mlx5_sf_hwc_free: trace freeing of the hardware SF context::
196 - mlx5_sf_hwc_deferred_free: trace deferred freeing of the hardware SF context::
203 - mlx5_sf_update_state: trace state updates for SF contexts::
210 - mlx5_sf_vhca_event: trace SF vhca event and state::
[all …]
/linux/Documentation/networking/devlink/
H A Ddevlink-port.rst39 subfunction (SF).
145 The configured MAC address of the PCI VF/SF will be used by netdevice and rdma
146 device created for the PCI VF/SF.
164 - Get the MAC address of the SF identified by its unique devlink port index::
171 - Set the MAC address of the SF identified by its unique devlink port index::
184 When RoCE capability is disabled, it saves system memory per PCI VF/SF.
186 When user disables RoCE capability for a VF/SF, user application cannot send or
187 receive any RoCE packets through this VF/SF and RoCE GID table for this PCI
191 VF/SF driver cannot override it.
303 When user sets maximum number of IO event queues for a SF or
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-auxiliary9 is requested and freed respectively for the PCI SF.
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dcrcc57d.c29 crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF); in crcc57d_set_src()
H A Dcrcc37d.c34 crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF); in crcc37d_set_src()
H A Dcrc907d.c53 crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SF(i)); in crc907d_set_src()
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c67 #define SF(reg_name, field_name, post_fix)\ macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c69 #define SF(reg_name, field_name, post_fix)\ macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c76 #define SF(reg_name, field_name, post_fix)\ macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c73 #define SF(reg_name, field_name, post_fix)\ macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c69 #define SF(reg_name, field_name, post_fix)\ macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_factory_dcn401.c49 #define SF(reg_name, field_name, post_fix)\ macro
/linux/Documentation/core-api/
H A Derrseq.rst31 | counter | SF | errno |

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